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公开(公告)号：US4727486A
公开(公告)日：1988-02-23
申请号：US858786
申请日：1986-05-02
申请人： Michael D. Smith , Llewelyn S. Dunwell , Richard A. Lemay , Robert C. Miller , Theodore R. Staplin, Jr. , William E. Woods , John L. Curley
发明人： Michael D. Smith , Llewelyn S. Dunwell , Richard A. Lemay , Robert C. Miller , Theodore R. Staplin, Jr. , William E. Woods , John L. Curley
CPC分类号： G06F12/1054
摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.
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公开(公告)号：US4245299A
公开(公告)日：1981-01-13
申请号：US867262
申请日：1978-01-05
CPC分类号： G06F13/378 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle. Logic is provided in the first unit to enable the first unit to accept less parts of data than originally requested in the multiple fetch request. This permits the first unit to make multiple fetch requests of other units on the bus without regard to whether the other units are capable of performing multiple fetch operations and eliminates the need for abnormal condition recovery logic in the second unit. Logic is also provided to permit the first unit to utilize each part of data as it is received by the first unit without requiring the first unit to wait for the last transfer cycle before using any of the received parts of data.
摘要翻译： 在包括诸如数据处理系统之类的多个单元连接的公共总线的系统中，在异步生成的总线传送周期期间，信息可以由最高优先级单元传送。 逻辑被提供用于使第一单元（例如中央处理器）能够在第一传送周期期间进行诸如存储器的第二单元的多次提取请求。 多次提取请求请求第二单元在多个其它传送周期期间将多个数据部分传送到第一单元，其中在每个进一步的传送周期中传送一部分数据。 在第二单元中提供逻辑以使第二单元能够向第一单元指示，除了在最后一个进一步的传送周期内，每个进一步的传送周期将跟随另一传送周期。 在第一单元中提供逻辑以使得第一单元能够接收比原来在多次提取请求中要求的更少的数据部分。 这允许第一单元在总线上进行其他单元的多个提取请求，而不考虑其他单元是否能够执行多次获取操作，并且不需要第二单元中的异常状态恢复逻辑。 还提供逻辑以允许第一单元利用第一单元接收的数据的每个部分，而不需要第一单元在使用任何接收的数据部分之前等待最后的传送周期。
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公开(公告)号：US4472773A
公开(公告)日：1984-09-18
申请号：US302897
申请日：1981-09-16
CPC分类号： G06F9/30
摘要： A decoding logic system in a logic control system of a data processing system is disclosed, wherein the data processing system is comprized of a main memory unit communicating with the logic control system by way of a common communication bus, and wherein the logic control system and a CPU (central processing unit) communicate by way of a local communication bus. In response to a CPU request, CPU instructions stored in the main memory unit are received by the logic decoding system, and presented to the CPU in such a manner as to accommodate both memory bit and CPU computed bit modifications to the instructions during instruction execution, while avoiding interruptions in CPU activity caused by information transfer delays internal to the logic decoding system. Instruction modification also may be effected by incrementing or decrementing the instructions under firmware control.
摘要翻译： 公开了一种数据处理系统的逻辑控制系统中的解码逻辑系统，其中数据处理系统由与公共通信总线与逻辑控制系统通信的主存储单元组成，其中逻辑控制系统和 CPU（中央处理单元）通过本地通信总线进行通信。 响应于CPU请求，存储在主存储器单元中的CPU指令由逻辑解码系统接收，并且以在指令执行期间容纳存储器位和CPU计算的位修改的方式呈现给CPU， 同时避免在逻辑解码系统内部的信息传输延迟引起的CPU活动中断。 也可以通过在固件控制下增加或减少指令来实现指令修改。
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4.发明授权Automatic operand length control of the result of a scientific arithmetic operation 失效自动操作数长度控制的科学算术运算结果
公开(公告)号：US4305134A
公开(公告)日：1981-12-08
申请号：US92619
申请日：1979-11-08
CPC分类号： G06F7/483 , G06F7/49947
摘要： Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a second address location of the random access memory. The mantissa result is truncated by addressing the high order 24 bits at the first address location and the 48 binary ZEROs at the second address location.
摘要翻译： 通过将64位尾数结果存储在随机存取存储器的第一地址位置中，将浮点运算的尾数结果截断为24位的字，并将二进制ZERO存储在第二地址位置的48个最低有效位位置 随机存取存储器。 通过寻址第一个地址位置的高位24位和第二个地址位置的48个二进制ZERO来截断尾数结果。
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5.发明授权Method for organizing state machine by selectively grouping status signals as inputs and classifying commands to be executed into performance sensitive and nonsensitive categories 失效通过选择性地将状态信号分组为输入并将待执行的命令分类为性能敏感和非敏感类别来组织状态机的方法
公开(公告)号：US5375248A
公开(公告)日：1994-12-20
申请号：US99117
申请日：1993-07-29
摘要： A virtual memory unit (VMU) includes a state machine for controlling its operations in response to commands received from another unit. The state machine includes a plurality of programmable array logic (PAL) devices which are connected to gather status from the different sections of the unit. The outputs of the PAL devices connect in common and supply a first address input to an addressable state memory. The state memory includes a plurality of locations, each of which stores a binary code defining a different machine state. The state memory locations are accessed as a function of the status signals and current state and used in turn to generate the required subcommands for executing the received commands. The state machine makes it possible to easily classify the received commands to their complexity and urgency in terms of their effect on overall system performance.
摘要翻译： 虚拟存储器单元（VMU）包括用于响应于从另一单元接收的命令来控制其操作的状态机。 状态机包括多个可编程阵列逻辑（PAL）装置，其被连接以从该装置的不同部分收集状态。 PAL设备的输出共同连接，并将第一地址输入提供给可寻址状态存储器。 状态存储器包括多个位置，每个位置存储限定不同机器状态的二进制代码。 根据状态信号和当前状态访问状态存储器位置，并依次使用生成用于执行接收到的命令的必需子命令。 状态机使得可以在接收到的命令的整体系统性能方面对其复杂性和紧迫性进行分类。
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6.发明授权Buffered address stack register with parallel input registers and overflow protection 失效缓冲地址堆栈寄存器具有并行输入寄存器和溢出保护
公开(公告)号：US5161217A
公开(公告)日：1992-11-03
申请号：US418084
申请日：1989-10-06
IPC分类号： G06F7/78
CPC分类号： G06F7/78
摘要： A last-in, first-out register having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the addresses already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be retransferred to the buffer address register for read out.
摘要翻译： 一个具有多个地址输入端口并且能够存储多个地址的先进先出寄存器。 地址加载操作与地址读取操作重叠，以加快地址可以从寄存器存储和检索的速率。 当寄存器充满地址时，它提供一个指示，允许：已经存储在寄存器中的地址被读出并存储在外部存储器中，然后存储在寄存器中的附加地址，以及随后传送到存储器的地址 用于存储重新发送到缓冲地址寄存器以进行读出。
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公开(公告)号：US4837738A
公开(公告)日：1989-06-06
申请号：US927631
申请日：1986-11-05
IPC分类号： G06F12/04
CPC分类号： G06F12/04
摘要： An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.
摘要翻译： 公开了一种地址边界检测器，其在计算机处理器中与算术逻辑单元（ALU）一起工作，而ALU通过向基址添加偏移或位移来生成地址。 检测器监视地址位，以确定数据项是否可以完全存储在与从其导出的基址所寻址的存储器相同的块或页内。
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8.发明授权Two stage selection based on time of arrival and predetermined priority in a bus priority resolver 失效基于总线优先级解算器的到达时间和预定优先级的两级选择
公开(公告)号：US4604685A
公开(公告)日：1986-08-05
申请号：US659012
申请日：1984-10-09
CPC分类号： G06F13/18
摘要： A priority resolver for providing unambiguous resolution of requests among competing processes vying for access to a common device and which is adapted to a non-distributed environment.
摘要翻译： 一种优先级解析器，用于在争夺访问公共设备的竞争过程中提供明确的请求解决方案，并适用于非分布式环境。
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公开(公告)号：US4451883A
公开(公告)日：1984-05-29
申请号：US326260
申请日：1981-12-01
CPC分类号： G06F9/30032 , G06F9/30167
摘要： A data processing system includes a memory subsystem for storing operands and instructions and a central processing unit (CPU) for manipulating the operands by executing the instructions. The CPU includes a control store for generating signals for controlling the CPU operation. Shifters made up of multiplexers shift operands between an outer bus and a write bus in response to control store signals. The multiplexers shift the operands left or right 1, 2 or 4-bit positions including open shifts and circular shifts and also perform byte position shifting and twinning.
摘要翻译： 数据处理系统包括用于存储操作数和指令的存储器子系统和用于通过执行指令来操纵操作数的中央处理单元（CPU）。 CPU包括用于产生用于控制CPU操作的信号的控制存储器。 由复用器组成的移位器响应于控制存储信号在外部总线和写入总线之间移动操作数。 多路复用器将操作数向左或向右移位1,2或4位位置，包括开位移和循环移位，并且还执行字节位移和孪生。
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公开(公告)号：US4964037A
公开(公告)日：1990-10-16
申请号：US19898
申请日：1987-02-27
IPC分类号： G06F12/06
CPC分类号： G06F12/0623
摘要： A memory address controller addresses two memories and selectively modifies an address before it is applied to the addressing input of one of the two memories. A bit of the address is used to indicate to the controller if the address is to be modified. The same address is applied unchanged to the addressing input of the other of the two memories by the memory address controller. In this manner the addressing range is expanded.
摘要翻译： 存储器地址控制器寻址两个存储器，并且在将地址应用于两个存储器之一的寻址输入之前选择性地修改地址。 地址的一部分用于向控制器指示是否要修改地址。 通过存储器地址控制器将相同的地址不变地应用于两个存储器中的另一个的寻址输入。 以这种方式扩展了寻址范围。
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