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193 条记录 (耗时 0.023 秒)

    Pattern layout of transfer transistors employed in a row decoder
    1.
    发明授权
    Pattern layout of transfer transistors employed in a row decoder 失效
    在行解码器中使用的转移晶体管的图案布局

    公开(公告)号：US06690596B2

    公开(公告)日：2004-02-10

    申请号：US10303946

    申请日：2002-11-26

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    IPC分类号： G11C506

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

    摘要： A semiconductor memory device comprising a memory cell array and a word-line select circuit. The memory cell array having first to third word lines connected to first to third groups of memory cells, respectively. The second word lines are adjacent to the first word lines. The word-line select circuit selects at least one row of memory cells. The word-line select circuit includes first to third groups of word-line select transistors arranged in row and column directions. The first to third groups of word-line select transistors are connected to the first to third word line, respectively. The third group of word-line select transistors are each arranged interposed between any adjacent two of the first and second group of word-line select transistors.

    摘要翻译： 一种半导体存储器件，包括存储单元阵列和字线选择电路。 存储单元阵列具有分别连接到第一至第三组存储器单元的第一至第三字线。 第二字线与第一字线相邻。 字线选择电路选择至少一行存储单元。 字线选择电路包括以行和列方向布置的第一至第三组字线选择晶体管。 第一至第三组字线选择晶体管分别连接到第一至第三字线。 第三组字线选择晶体管分别布置在第一和第二组字线选择晶体管中的任何相邻的两个之间。

    Pattern layout of transfer transistors employed in row decoder
    2.
    发明授权
    Pattern layout of transfer transistors employed in row decoder 失效

    公开(公告)号：US06507508B2

    公开(公告)日：2003-01-14

    申请号：US09984960

    申请日：2001-10-31

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    IPC分类号： G11C506

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

    摘要： A semiconductor memory device comprises a memory cell array, a block select circuit, a plurality of word-line-driving-signal lines, and a plurality of transfer transistors. The memory cell array includes a plurality of blocks, each of the blocks including memory cells arranged in rows and columns. The block select circuit selects one of the blocks of the memory cell array. The word-line-driving-signal lines receive voltages to be applied to a plurality of word lines in each block. The transfer transistors are connected between the word-line-driving-signal lines and the word lines of the memory cell array, and are controlled by outputs from the block select circuit. Any two of the transfer transistors, which correspond to each pair of adjacent ones of the word lines, are separate from each other lengthwise and widthwise, and one or more transfer transistors corresponding to another word line or other word lines are interposed therebetween.

    Fail number detecting circuit of flash memory
    4.
    发明授权
    Fail number detecting circuit of flash memory 有权
    闪存的故障号检测电路

    公开(公告)号：US06859401B2

    公开(公告)日：2005-02-22

    申请号：US10674404

    申请日：2003-10-01

    申请人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    发明人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G11C29/12

    CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    摘要： A semiconductor device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes NAND cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current varying in proportion to “1” or “0” of binary logic data of one end of the plurality of latch circuits. The second circuit generates a second current which is preset. The third circuit compares the first current with the second current. The value of “1” or “0” of binary logic data of the one end of the plurality of latch circuits is detected based on a result of the comparison between the first current and the second current.

    摘要翻译： 半导体器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。 存储单元阵列包括其中布置的NAND单元。 锁存电路暂时保存从存储单元阵列读出的数据。 第一电路产生与多个锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。 第二电路产生预置的第二电流。 第三电路将第一电流与第二电流进行比较。 基于第一电流和第二电流之间的比较结果，检测多个锁存电路一端的二进制逻辑数据的“1”或“0”值。

    Pattern layout of transfer transistors employed in row decoder
    5.
    发明申请
    Pattern layout of transfer transistors employed in row decoder 失效
    在行解码器中使用的转移晶体管的图案布局

    公开(公告)号：US20050018462A1

    公开(公告)日：2005-01-27

    申请号：US10922950

    申请日：2004-08-23

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    IPC分类号： H01L21/8247 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C19/08

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

    摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and is configured to transfer a plurality of different voltages to word lines through current paths of the transfer transistors and select memory cells of at least one row of said plurality of blocks. The transfer transistors include a first group, which transfers the lowest voltage of voltages applied to the word lines in a writing operation and a second group, which is arranged not to be adjacent to the first group and transfers the highest voltage of voltages applied to the word lines in a writing operation.

    摘要翻译： 半导体器件包括存储单元阵列和字线选择电路。 存储单元阵列包括以行和列排列的多个存储单元。 存储单元阵列包括其中每个存储单元被布置的多个块。 字线选择电路包括以列和列方向布置的传输晶体管，并且被配置为通过传输晶体管的电流路径将多个不同的电压传送到字线，并且选择所述多个块的至少一行的存储单元 。 转移晶体管包括第一组，其在写入操作中传送施加到字线的最低电压电压，第二组被布置为不与第一组相邻，并且传送施加到第一组的最高电压电压 写字操作中的字线。

    Fail number detecting circuit of flash memory
    6.
    发明授权
    Fail number detecting circuit of flash memory 有权
    闪存的故障号检测电路

    公开(公告)号：US06657896B2

    公开(公告)日：2003-12-02

    申请号：US10315050

    申请日：2002-12-10

    申请人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    发明人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    IPC分类号： G11C1606

    CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    摘要： A semiconductor memory device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes electrically rewritable nonvolatile memory cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current which varies in proportion to “1” or “0” of binary logical data of one end of the latch circuits. The second circuit generates a predetermined second current. The current control circuit is connected to the first and second circuits, and configured to determined absolute values of the first and second currents. The third circuit is configured to compare the first and second currents. The number of binary logical data of “1” or “0” of one end of the latch circuits is detected based on the result of comparison between the first and second currents.

    摘要翻译： 半导体存储器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。 存储单元阵列包括布置在其中的电可重写非易失性存储单元。 锁存电路暂时保存从存储单元阵列读出的数据。 第一电路产生与锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。 第二电路产生预定的第二电流。 电流控制电路连接到第一和第二电路，并被配置为确定第一和第二电流的绝对值。 第三电路被配置为比较第一和第二电流。 基于第一和第二电流之间的比较结果来检测锁存电路的一端的“1”或“0”的二进制逻辑数据的数量。

    Pattern layout of transfer transistors employed in row decoder
    7.
    发明授权
    Pattern layout of transfer transistors employed in row decoder 失效
    在行解码器中使用的转移晶体管的图案布局

    公开(公告)号：US06798683B2

    公开(公告)日：2004-09-28

    申请号：US10706909

    申请日：2003-11-14

    申请人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    发明人： Koji Hosono ,  Hiroshi Nakamura ,  Kenichi Imamiya ,  Tomoharu Tanaka

    IPC分类号： G11C506

    CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/08

    摘要： A semiconductor device comprises a memory cell array and a word-line select circuit. The memory cell array includes a plurality of memory cells arranged in rows and columns, the memory cell array having a plurality of blocks in each one of which the memory cells are arranged. The word-line select circuit includes transfer transistors arranged in row and column directions, and configured to select at least one row of memory cells from the plurality of memory cells in a block. The word-line select circuit includes first transistors to which OV is to be applied, second transistors to which an intermediate level voltage is to be applied, the intermediate voltage being a voltage applied to a non-selected word line in a block selected in a writing operation, third transistors to which a write voltage is to be applied, the third transistors being separated from the first transistors.

    摘要翻译： 半导体器件包括存储单元阵列和字线选择电路。 存储单元阵列包括排列成行和列的多个存储单元，存储单元阵列具有排列有存储单元的每一个中的多个块。 字线选择电路包括以行和列方向布置的传输晶体管，并且被配置为从块中的多个存储器单元中选择至少一行存储器单元。 字线选择电路包括要被施加0V的第一晶体管，要施加中间电平电压的第二晶体管，中间电压是施加到在所选择的块中的未选择字线的电压 写入操作，施加写入电压的第三晶体管，第三晶体管与第一晶体管分离。