NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD
    1.
    发明申请
    NOVEL HIGH-K METAL GATE CMOS PATTERNING METHOD 有权
    新型高K金属栅CMOS图案方法

    公开(公告)号:US20100048013A1

    公开(公告)日:2010-02-25

    申请号:US12536629

    申请日:2009-08-06

    IPC分类号: H01L21/28

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底,在半导体衬底上形成高k电介质层,在高k电介质层上形成覆盖层,在覆盖层上形成第一金属层 第一金属层具有第一功函数,在第一有源区中的第一金属层上形成掩模层,使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分 并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层,所述第二金属层具有第二功函数。

    High-k metal gate CMOS patterning method
    2.
    发明授权
    High-k metal gate CMOS patterning method 有权
    高k金属栅极CMOS图案化方法

    公开(公告)号:US08349680B2

    公开(公告)日:2013-01-08

    申请号:US12536629

    申请日:2009-08-06

    IPC分类号: H01L21/8238

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底,在半导体衬底上形成高k电介质层,在高k电介质层上形成覆盖层,在覆盖层上形成第一金属层 第一金属层具有第一功函数,在第一有源区中的第一金属层上形成掩模层,使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分 并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层,所述第二金属层具有第二功函数。

    Integrated high-K/metal gate in CMOS process flow
    3.
    发明授权
    Integrated high-K/metal gate in CMOS process flow 有权
    CMOS工艺流程中集成的高K /金属栅极

    公开(公告)号:US08383502B2

    公开(公告)日:2013-02-26

    申请号:US13186572

    申请日:2011-07-20

    IPC分类号: H01L21/3205 H01L21/4763

    摘要: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

    摘要翻译: 制造半导体器件的方法包括提供具有第一有源区和第二有源区的半导体衬底,在高k电介质层上形成第一金属层,去除第二有源区中的第一金属层的至少一部分 在第一有源区的第一金属层上形成第二金属层,在第二有源区的高k电介质层上形成第二金属层,然后在第二金属层上形成硅层。 该方法还包括从第一栅极堆叠中去除硅层,从而形成第一沟槽并从第二栅极堆叠形成第二沟槽,并且在第一沟槽中的第二金属层上方形成第三金属层,并在第二金属 在第二沟槽中。

    Integrated High-K/Metal Gate in CMOS Process Flow
    4.
    发明申请
    Integrated High-K/Metal Gate in CMOS Process Flow 有权
    CMOS工艺流程中集成的高K /金属门

    公开(公告)号:US20110275212A1

    公开(公告)日:2011-11-10

    申请号:US13186572

    申请日:2011-07-20

    IPC分类号: H01L21/28

    摘要: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.

    摘要翻译: 制造半导体器件的方法包括提供具有第一有源区和第二有源区的半导体衬底,在高k电介质层上形成第一金属层,去除第二有源区中的第一金属层的至少一部分 在第一有源区的第一金属层上形成第二金属层,在第二有源区的高k电介质层上形成第二金属层,然后在第二金属层上形成硅层。 该方法还包括从第一栅极堆叠中去除硅层,从而形成第一沟槽并从第二栅极堆叠形成第二沟槽,并且在第一沟槽中的第二金属层上方形成第三金属层,并在第二金属 在第二沟槽中。

    Method of integrating high-K/metal gate in CMOS process flow
    5.
    发明授权
    Method of integrating high-K/metal gate in CMOS process flow 有权
    在CMOS工艺流程中集成高K /金属栅极的方法

    公开(公告)号:US08003507B2

    公开(公告)日:2011-08-23

    申请号:US12478509

    申请日:2009-06-04

    IPC分类号: H01L21/3205 H01L21/4763

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底,在半导体衬底上形成高k电介质层,在高k电介质层上形成第一金属层,第一金属层具有第一 在第二有源区中除去第一金属层的一部分,然后在第一有源区中的第一金属层上方和在第二有源区中的部分去除的第一金属层上方形成半导体层,形成第一 在第一有源区中的栅极堆叠和第二有源区中的第二栅极堆叠,从第一栅极堆叠和第二栅极堆叠中去除半导体层,以及在第一栅极堆叠中的第一金属层上形成第二金属层 并且在第二栅极堆叠中部分去除的第一金属层上,第二金属层具有第二功函数。

    METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW
    6.
    发明申请
    METHOD OF INTEGRATING HIGH-K/METAL GATE IN CMOS PROCESS FLOW 有权
    在CMOS工艺流程中集成高K /金属栅的方法

    公开(公告)号:US20100041223A1

    公开(公告)日:2010-02-18

    申请号:US12478509

    申请日:2009-06-04

    IPC分类号: H01L21/28

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer over the high-k dielectric layer, the first metal layer having a first work function, removing a portion of the first metal layer in the second active region, thereafter, forming a semiconductor layer over the first metal layer in the first active region and over the partially removed first metal layer in the second active region, forming a first gate stack in the first active region and a second gate stack in the second active region, removing the semiconductor layer from the first gate stack and from the second gate stack, and forming a second metal layer on the first metal layer in the first gate stack and on the partially removed first metal layer in the second gate stack, the second metal layer having a second work function.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底,在半导体衬底上形成高k电介质层,在高k电介质层上形成第一金属层,第一金属层具有第一 在第二有源区中除去第一金属层的一部分,然后在第一有源区中的第一金属层上方和在第二有源区中的部分去除的第一金属层上方形成半导体层,形成第一 在第一有源区中的栅极堆叠和第二有源区中的第二栅极堆叠,从第一栅极堆叠和第二栅极堆叠中去除半导体层,以及在第一栅极堆叠中的第一金属层上形成第二金属层 并且在第二栅极堆叠中部分去除的第一金属层上,第二金属层具有第二功函数。

    Method for semiconductor device performance enhancement
    7.
    发明授权
    Method for semiconductor device performance enhancement 有权
    半导体器件性能提高的方法

    公开(公告)号:US07632729B2

    公开(公告)日:2009-12-15

    申请号:US11527616

    申请日:2006-09-27

    IPC分类号: H01L21/8238

    摘要: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

    摘要翻译: 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分,并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

    Method for semiconductor device performance enhancement
    8.
    发明申请
    Method for semiconductor device performance enhancement 有权
    半导体器件性能提高的方法

    公开(公告)号:US20080076215A1

    公开(公告)日:2008-03-27

    申请号:US11527616

    申请日:2006-09-27

    IPC分类号: H01L21/8238

    摘要: A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

    摘要翻译: 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分,并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

    METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS
    9.
    发明申请
    METHOD OF FORMING A SINGLE METAL THAT PERFORMS N WORK FUNCTION AND P WORK FUNCTION IN A HIGH-K/METAL GATE PROCESS 有权
    在高K /金属浇口工艺中形成单一金属的方法,其具有N个工作功能和P功能

    公开(公告)号:US20100038721A1

    公开(公告)日:2010-02-18

    申请号:US12492889

    申请日:2009-06-26

    IPC分类号: H01L27/092 H01L21/28

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极电介质,在栅极电介质之上或之下形成覆盖层,在覆盖层上形成金属层,金属层具有第一功函数,处理金属层的一部分,使得 所述金属层的所述部分的功函数从所述第一功函数变为第二功函数,并且从具有所述第一功函数的所述金属层的未处理部分形成第一金属栅极,并且从所述处理的所述金属栅极形成第二金属栅极 具有第二功函数的金属层的部分。

    Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process
    10.
    发明授权
    Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process 有权
    在高k /金属栅极工艺中形成执行N功函数和P功函数的单一金属的方法

    公开(公告)号:US08524588B2

    公开(公告)日:2013-09-03

    申请号:US12492889

    申请日:2009-06-26

    IPC分类号: H01L21/3205 H01L21/4763

    摘要: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate dielectric over a semiconductor substrate, forming a capping layer over or under the gate dielectric, forming a metal layer over the capping layer, the metal layer having a first work function, treating a portion of the metal layer such that a work function of the portion of the metal layer changes from the first work function to a second work function, and forming a first metal gate from the untreated portion of the metal layer having the first work function and forming a second metal gate from the treated portion of the metal layer having the second work function.

    摘要翻译: 本公开提供了制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极电介质,在栅极电介质上或之下形成覆盖层,在覆盖层上形成金属层,金属层具有第一功函数,处理金属层的一部分,使得 所述金属层的所述部分的功函数从所述第一功函数变化为第二功函数,并且从具有所述第一功函数的所述金属层的未处理部分形成第一金属栅极,并且从所述处理的所述第二金属栅极形成第二金属栅极 具有第二功函数的金属层的部分。