Spike pulse generation circuit comprising single silicon device

    公开(公告)号:US11444606B2

    公开(公告)日:2022-09-13

    申请号:US17168395

    申请日:2021-02-05

    Abstract: Provided is a spike pulse generation circuit comprising a single silicon device configured to non-periodically or periodically generate a spike pulse. More particularly, the spike pulse generation circuit comprising the single silicon device can utilize a positive feedback loop and a negative feedback loop to be mutually connected so as to selectively output a spike pulse related to a neural oscillation function similar to biological oscillation, thereby being capable of serving as a ring oscillator and performing a neuron function operation.

    Thermoelectric generator module and method for manufacturing the same

    公开(公告)号:US09876156B2

    公开(公告)日:2018-01-23

    申请号:US14845728

    申请日:2015-09-04

    CPC classification number: H01L35/32 H01L35/34

    Abstract: The present invention provides a thermoelectric generator module including a set of module unit bodies disposed between a hot source and a cold source to serve as fundamental structures for performing thermoelectric power generation and a method of manufacturing the thermoelectric generator module. Each of the module unit bodies comprises: a first electrodes disposed at one of the hot source and the cold source; a second electrode disposed at the other of the hot source and the cold source so as to be spaced apart from the first electrodes; a first nanowire configured to interconnect the first electrode and the second electrode and composed of an n-type or p-type semiconductor; and a second nanowire.

    Logic-in-memory inverter using feedback field-effect transistor

    公开(公告)号:US11695420B2

    公开(公告)日:2023-07-04

    申请号:US17411353

    申请日:2021-08-25

    CPC classification number: H03K19/01714 H01L27/0922 H01L29/0665 H03K19/0013

    Abstract: Disclosed is technology that is driven using a positive feedback loop of a feedback field-effect transistor and is capable of performing a logic-in memory function. The logic-in-memory inverter includes a metal oxide semiconductor field-effect transistor, and a feedback field-effect transistor in which a drain region of a nanostructure is connected in series to a drain region of the metal oxide semiconductor field-effect transistor, wherein the logic-in-memory inverter performs a logical operation is performed based on an output voltage VOUT that changes depending on a level of an input voltage VIN that is input to a gate electrode of the feedback field-effect transistor and a gate electrode of the metal oxide semiconductor field-effect transistor while a source voltage VSS is input to a source region of the nanostructure and a drain voltage VDD is input to a source region of the metal oxide semiconductor field-effect transistor.

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