公开(公告)号：US20110272753A1

公开(公告)日：2011-11-10

申请号：US13144744

申请日：2009-10-23

申请人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

发明人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L29/792 ,  H01L21/8239 ,  H01L21/336 ,  H01L27/06 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

摘要翻译： 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US08633530B2

公开(公告)日：2014-01-21

申请号：US13144744

申请日：2009-10-23

申请人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

发明人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L21/28 ,  H01L29/792 ,  H01L21/336 ,  H01L27/06

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/0653 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a power feeding region of a memory cell (MC) in which a sidewall-shaped memory gate electrode (MG) of a memory nMIS (Qnm) is provided by self alignment on a side surface of a selection gate electrode (CG) of a selection nMIS (Qnc) via an insulating film, a plug (PM) which supplies a voltage to the memory gate electrode (MG) is embedded in a contact hole (CM) formed in an interlayer insulating film (9) formed on the memory gate electrode (MG) and is electrically connected to the memory gate electrode (MG). Since a cap insulating film (CAP) is formed on an upper surface of the selection gate electrode (CG), the electrical conduction between the plug (PM) and the selection gate electrode (CG) can be prevented.

摘要翻译： 在存储单元（MC）的馈电区域中，在存储单元（MC）的馈电区域中，通过自对准在存储器nMIS（Qnm）的选择栅极（CG）的侧表面上提供存储器nMIS（Qnm）的侧壁形状的存储栅极（MG） 通过绝缘膜选择nMIS（Qnc），向存储栅电极（MG）提供电压的插头（PM）嵌入在形成在存储栅上的层间绝缘膜（9）中形成的接触孔（CM） 电极（MG）并且电连接到存储栅电极（MG）。 由于在选择栅电极（CG）的上表面上形成帽绝缘膜（CAP），所以可以防止插头（PM）与选择栅电极（CG）之间的导电。

公开(公告)号：US09093319B2

公开(公告)日：2015-07-28

申请号：US13468992

申请日：2012-05-10

申请人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

发明人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L29/94 ,  H01L27/115 ,  H01L27/105 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423 ,  H01L29/792 ,  G11C16/04 ,  H01L29/66

CPC分类号： H01L27/11563 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/4234 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/792

摘要： A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

摘要翻译： 在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。 存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜 一部分。 电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极 薄膜作为记忆栅电极。 上部电极的杂质浓度高于记忆栅电极的浓度。

公开(公告)号：US08969943B2

公开(公告)日：2015-03-03

申请号：US13302184

申请日：2011-11-22

申请人： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

发明人： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

摘要翻译： 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US08569144B2

公开(公告)日：2013-10-29

申请号：US13365183

申请日：2012-02-02

申请人： Kota Funayama ,  Hiraku Chakihara

发明人： Kota Funayama ,  Hiraku Chakihara

IPC分类号： H01L21/76 ,  G03C5/18

CPC分类号： H01L21/76229 ,  G11C16/0425 ,  G11C16/0433 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/792

摘要： In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.

摘要翻译： 在本发明中，在曝光于半导体存储器等的存储单元阵列等的光时，当用于蚀刻STI沟槽区域的一组单位开口，其中用于蚀刻每个STI沟槽区域的单位开口 具有矩形形状的行和列通过曝光被转印到负的抗蚀剂膜上，适当地使用多次曝光，其包括使用具有在列方向上延伸的第一线性开口的组的第一光学掩模的第一曝光步骤，以及 使用具有在行方向上延伸的一组第二线性开口的第二光学掩模的第二曝光步骤。

公开(公告)号：US20120132978A1

公开(公告)日：2012-05-31

申请号：US13302184

申请日：2011-11-22

申请人： Koichi TOBA ,  Yasushi Ishi ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

发明人： Koichi TOBA ,  Yasushi Ishi ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

摘要翻译： 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US08133795B2

公开(公告)日：2012-03-13

申请号：US12956338

申请日：2010-11-30

申请人： Kota Funayama ,  Hiraku Chakihara

发明人： Kota Funayama ,  Hiraku Chakihara

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  G11C16/0425 ,  G11C16/0433 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/792

摘要： In the present invention, in the exposure to light of a memory cell array or the like of a semiconductor memory or the like, when a group of unit openings for etching the STI trench regions in which the unit openings for etching the STI trench regions each having a rectangular shape are arranged in rows and columns are transferred by the exposure onto a negative resist film, multiple exposure is appropriately used which includes a first exposure step using a first optical mask having a group of first linear openings extending in a column direction and a second exposure step using a second optical mask having a group of second linear openings extending in a row direction.

摘要翻译： 在本发明中，在曝光于半导体存储器等的存储单元阵列等的光时，当用于蚀刻STI沟槽区域的一组单位开口，其中用于蚀刻每个STI沟槽区域的单位开口 具有矩形形状的行和列通过曝光被转印到负的抗蚀剂膜上，适当地使用多次曝光，其包括使用具有在列方向上延伸的第一线性开口的组的第一光学掩模的第一曝光步骤，以及 使用具有在行方向上延伸的一组第二线性开口的第二光学掩模的第二曝光步骤。

公开(公告)号：US08461642B2

公开(公告)日：2013-06-11

申请号：US12534140

申请日：2009-08-02

申请人： Takuro Homma ,  Yasushi Ishii ,  Kota Funayama

发明人： Takuro Homma ,  Yasushi Ishii ,  Kota Funayama

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11573 ,  H01L27/11 ,  H01L27/1104

摘要： The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.

摘要翻译： 本发明可以实现具有配备有分离栅极结构的MONOS型非易失性存储单元的高度集成的半导体器件，而不会降低器件的可靠性。 存储器nMIS的存储栅电极具有比选择nMIS的选择栅电极高20至100nm的高度，使得形成在一个侧面（源区侧面上的侧表面）的侧壁的宽度 将存储栅电极的侧表面调节到实现所需干扰特性所需的宽度。 此外，外围第二nMIS的栅电极具有不大于选择nMIS的选择栅电极的高度的高度，以减小形成在周边第二nMIS的栅电极的侧表面上的侧壁的宽度，所以 防止共享的接触孔被侧壁填充。

公开(公告)号：US20100059810A1

公开(公告)日：2010-03-11

申请号：US12534140

申请日：2009-08-02

申请人： Takuro HOMMA ,  Yasushi Ishii ,  Kota Funayama

发明人： Takuro HOMMA ,  Yasushi Ishii ,  Kota Funayama

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11573 ,  H01L27/11 ,  H01L27/1104

摘要： The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.

摘要翻译： 本发明可以实现具有配备有分离栅极结构的MONOS型非易失性存储单元的高度集成的半导体器件，而不会降低器件的可靠性。 存储器nMIS的存储栅电极具有比选择nMIS的选择栅电极的高20至100nm的高度，使得形成在一个侧面（源区侧面上的侧表面）的侧壁的宽度 将存储栅电极的侧表面调节到实现所需干扰特性所需的宽度。 此外，外围第二nMIS的栅电极具有不大于选择nMIS的选择栅电极的高度的高度，以减小形成在周边第二nMIS的栅电极的侧表面上的侧壁的宽度，所以 防止共享的接触孔被侧壁填充。

公开(公告)号：US06943373B2

公开(公告)日：2005-09-13

申请号：US10693987

申请日：2003-10-28

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Riichiro Takemura ,  Kousuke Okuyama ,  Masahiro Moniwa ,  Akio Nishida ,  Kota Funayama ,  Tomonori Sekiguchi

IPC分类号： G11C11/41 ,  H01L21/8234 ,  H01L21/8244 ,  H01L27/00 ,  H01L27/06 ,  H01L27/088 ,  H01L27/10 ,  H01L27/11 ,  H01L29/10 ,  H01L29/72

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/1104

摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.