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356 条记录 (耗时 0.034 秒)

    Elevated source/drain field effect transistor and method for making the same
    1.
    发明授权
    Elevated source/drain field effect transistor and method for making the same 有权
    提高源/漏场效应晶体管及其制作方法

    公开(公告)号：US06677212B1

    公开(公告)日：2004-01-13

    申请号：US10070478

    申请日：2002-05-02

    申请人： Fumiyoshi Yoshioka ,  Masayuki Nakano ,  Hiroshi Iwata

    发明人： Fumiyoshi Yoshioka ,  Masayuki Nakano ,  Hiroshi Iwata

    IPC分类号： H01L27108

    CPC分类号： H01L29/66598 ,  H01L21/26586 ,  H01L21/28525 ,  H01L29/1083 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/6659

    摘要： A gate oxide film (23), a gate electrode (24) and a gate cap insulating film (25) are stacked on an active region of a p-type semiconductor substrate (21), and an insulating side wall (29) is formed, followed by BF2 ion implantation. Thus, a surface of the p-type semiconductor substrate becomes amorphous so that single-crystal silicon is prevented from epitaxially growing in the next process of depositing polysilicon (33). Halo regions (32) are formed using the BF2 ions having the opposite conductivity to a source/drain to reduce the short-channel effect. The substrate is then passed through a nitrogen purge chamber having a dew point kept at −100° C. to remove water molecules completely, and polysilicon (33) is deposited. Because native oxide is prevented from growing at an interface between the active region and the polysilicon, source/drain regions (34) formed later by implantation and diffusion of n-type impurity ions achieve a uniform junction depth.

    摘要翻译： 在p型半导体基板（21）的有源区上层叠有栅极氧化膜（23），栅极电极（24）和栅极绝缘膜（25），形成绝缘侧壁（29） ，然后进行BF2离子注入。 因此，p型半导体衬底的表面变为非晶态，从而在下一个沉积多晶硅的工艺中防止单晶硅外延生长（33）。 使用与源极/漏极具有相反导电性的BF 2离子形成光晕区域（32），以减少短沟道效应。 然后将基底通过具有保持在-100℃的露点的氮气净化室，以完全去除水分子，并沉积多晶硅（33）。 因为防止在有源区和多晶硅之间的界面处生长了自然氧化物，所以随后通过n型杂质离子的注入和扩散而形成的源/漏区（34）达到均匀的结深度。

    Semiconductor memory device and portable electronic apparatus
    2.
    发明授权
    Semiconductor memory device and portable electronic apparatus 有权
    半导体存储器件和便携式电子设备

    公开(公告)号：US07262458B2

    公开(公告)日：2007-08-28

    申请号：US10844471

    申请日：2004-05-13

    申请人： Fumiyoshi Yoshioka ,  Akihide Shibata ,  Hiroshi Iwata

    发明人： Fumiyoshi Yoshioka ,  Akihide Shibata ,  Hiroshi Iwata

    IPC分类号： H01L29/788

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/6684

    摘要： A semiconductor memory device includes: a gate electrode formed on a semiconductor layer via a gate insulating film; a channel region disposed under the gate electrode; diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region; and memory functional units formed on both sides of the gate electrode and having the function of retaining charges, wherein each of the diffusion regions has: a high-concentration impurity region disposed so as to be offset from the gate electrode; and a low-concentration impurity region disposed in contact with the high-concentration impurity region so as to overlap with the gate electrode, and an amount of current flowing from one of the diffusion regions to the other diffusion region is changed when a voltage is applied to the gate electrode in accordance with an amount of charges retained in the memory functional units.

    摘要翻译： 半导体存储器件包括：栅电极，经栅极绝缘膜形成在半导体层上; 设置在所述栅电极下方的沟道区域; 扩散区域设置在沟道区域的两侧并且具有与沟道区域的导电类型相反的导电类型; 以及存储功能单元，其形成在所述栅极电极的两侧并且具有保持电荷的功能，其中每个扩散区具有：设置成偏离所述栅电极的高浓度杂质区; 以及与高浓度杂质区域接触以与栅电极重叠的低浓度杂质区域，并且当施加电压时改变从一个扩散区域流向另一个扩散区域的电流量 根据保存在存储功能单元中的电荷量向栅极施加电压。

    Semiconductor storage device, manufacturing method therefor and portable electronic equipment
    5.
    发明授权
    Semiconductor storage device, manufacturing method therefor and portable electronic equipment 有权
    半导体存储装置及其制造方法及便携式电子设备

    公开(公告)号：US07315060B2

    公开(公告)日：2008-01-01

    申请号：US11142770

    申请日：2005-06-02

    申请人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

    发明人： Hiroshi Iwata ,  Akihide Shibata ,  Kotaro Kataoka ,  Masayuki Nakano

    IPC分类号： H01L29/792

    CPC分类号： H01L29/6684 ,  G11C16/0475 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

    摘要： A semiconductor storage device has a single gate electrode formed on a semiconductor substrate through a gate insulation film. First and second memory function bodies formed on both sides of the gate electrode. A P-type channel region is formed in a surface of the substrate on the side of the gate electrode. N-type first and second diffusion regions are formed on both sides of the channel region. The channel region is composed of an offset region located under the first and second memory function bodies and a gate electrode beneath region located under the gate electrode. The concentration of a dopant which imparts a P-type conductivity to the offset region is effectively lower than the concentration of a dopant which imparts the P-type conductivity to the gate electrode beneath region. This makes it possible to provide the semiconductor storage device which is easily shrunk in scale.

    摘要翻译： 半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的单个栅电极。 形成在栅电极两侧的第一和第二记忆功能体。 在栅极侧的基板的表面形成P型沟道区。 在沟道区域的两侧形成N型第一和第二扩散区域。 沟道区域由位于第一和第二存储器功能体下面的偏移区域和位于栅电极下方的栅极电极构成。 赋予偏移区域的P型导电性的掺杂剂的浓度有效地低于向区域下方的栅电极施加P型导电性的掺杂剂的浓度。 这使得可以提供容易缩小的半导体存储装置。

    Semiconductor device and method for producing the same
    9.
    发明授权
    Semiconductor device and method for producing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06682966B2

    公开(公告)日：2004-01-27

    申请号：US10171540

    申请日：2002-06-17

    申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

    发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

    IPC分类号： A01L2100

    CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

    摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

    摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。