公开(公告)号：US06297114B1

公开(公告)日：2001-10-02

申请号：US09205754

申请日：1998-12-04

申请人： Hiroshi Iwata ,  Masayuki Nakano ,  Seizo Kakimoto ,  Kouichirou Adachi ,  Satoshi Morishita

发明人： Hiroshi Iwata ,  Masayuki Nakano ,  Seizo Kakimoto ,  Kouichirou Adachi ,  Satoshi Morishita

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/0332 ,  H01L21/26586 ,  H01L21/28017 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833

摘要： A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity diffusion region. The above semiconductor device is able to suppress the short-channel effects, and reduce the source-drain parasitic resistance and the source-drain junction leakage current while maintaining a small source-drain capacity.

摘要翻译： 一种通过栅极氧化膜在Si衬底上具有栅电极的半导体器件; 具有与阱相反的导电类型的第一杂质扩散区，其将通过栅电极侧壁电介质膜在栅电极的两个相对侧中形成源区和漏区的一部分; 第二杂质扩散区，与栅电极侧壁电介质膜下方的第一杂质扩散区具有相同的导电类型，与栅电极正下方的沟道区相比，比第一杂质扩散区浅; 所述栅极电极上的钛硅化物膜和所述栅电极侧壁电介质膜的两个相对侧中的所述第一杂质扩散区域的所述Si衬底的表面; 和形成在第一杂质扩散区中的第三杂质扩散区，其具有比第一杂质扩散区高的浓度和与第一和第二杂质扩散区相同的导电类型。 上述半导体器件能够抑制短沟道效应，并且在保持较小的源极 - 漏极容量的同时降低源极 - 漏极寄生电阻和源极 - 漏极结漏电流。

公开(公告)号：US5976918A

公开(公告)日：1999-11-02

申请号：US985633

申请日：1997-12-04

申请人： Toshimasa Matsuoka ,  Masayuki Nakano ,  Satoshi Morishita ,  Hiroshi Iwata ,  Seizo Kakimoto ,  Takashi Fukushima

发明人： Toshimasa Matsuoka ,  Masayuki Nakano ,  Satoshi Morishita ,  Hiroshi Iwata ,  Seizo Kakimoto ,  Takashi Fukushima

IPC分类号： H01L29/78 ,  H01L21/314 ,  H01L21/318 ,  H01L21/324 ,  H01L21/00 ,  H01L21/20

CPC分类号： H01L21/3145

摘要： In accordance with the development of the fineness of MOSFETs, a gate insulating film and a capacitor insulating film are required to have a smaller thickness and a higher film quality. Accordingly, the present invention is intended to provide a method for forming a high-quality insulating film while preventing hydrogen atoms which cause a leak current and an electron trap from entering the insulating film. The present method uses a gas of molecules containing at least nitrogen, the gas is a compound which includes no oxygen atom and has no bond of a nitrogen atom and a hydrogen atom (N--H) and generates monoatomic nitrogen when the gas dissociates.

摘要翻译： 根据MOSFET的细度的发展，需要栅极绝缘膜和电容器绝缘膜具有更小的厚度和更高的膜质量。 因此，本发明旨在提供一种形成高品质绝缘膜的方法，同时防止引起漏电流的氢原子和电子陷阱进入绝缘膜。 本方法使用至少含有氮的分子气体，气体是不含氧原子的化合物，并且当气体解离时，不产生氮原子和氢原子（N-H）的键并产生单原子氮。

公开(公告)号：US07074676B2

公开(公告)日：2006-07-11

申请号：US10468738

申请日：2002-02-13

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Nobutoshi Arai ,  Takayuki Ogura ,  Kouichirou Adachi ,  Seizo Kakimoto ,  Yukio Yasuda ,  Shigeaki Zaima ,  Akira Sakai

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Nobutoshi Arai ,  Takayuki Ogura ,  Kouichirou Adachi ,  Seizo Kakimoto ,  Yukio Yasuda ,  Shigeaki Zaima ,  Akira Sakai

IPC分类号： H01L21/8247 ,  H01L29/788

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42332 ,  Y10S438/962

摘要： A memory film operable at a low voltage and a method of manufacturing the memory film; the method, comprising the steps of forming a first insulation film (112) on a semiconductor substrate (111) forming a first electrode, forming a first conductor film (113) on the first insulation film (112), forming a second insulation film (112B) on the surface of the first conductor film (113), forming a third insulation film containing conductor particulates (114, 115) on the second insulation film (112B), and forming a second conductor film forming a second electrode on the third insulation film.

摘要翻译： 以低电压工作的记忆膜和制造该记忆膜的方法; 该方法包括以下步骤：在形成第一电极的半导体衬底（111）上形成第一绝缘膜（112），在第一绝缘膜（112）上形成第一导体膜（113），形成第二绝缘膜（ 112B），在第二绝缘膜（112B）上形成包含导体微粒（114,115）的第三绝缘膜，并在第二绝缘膜（112B）上形成第二导电膜，形成第二电极 第三绝缘膜。

公开(公告)号：US06291861B1

公开(公告)日：2001-09-18

申请号：US09345414

申请日：1999-06-30

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/2257 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78654

摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.

摘要翻译： 具有器件分离区域和有源区域的半导体器件包括栅极氧化膜，源极/漏极区域和电耦合到源极/漏极区域的电极。 有源区在第一面处与栅极氧化膜接触，源/漏区的一部分位于第一面的上方。 电极在第二面处与源极/漏极区域接触，第二面部相对于第一面构成一个角度。

公开(公告)号：US06656799B2

公开(公告)日：2003-12-02

申请号：US10322492

申请日：2002-12-19

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/2257 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78654

摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.

摘要翻译： 具有器件分离区域和有源区域的半导体器件包括栅极氧化膜，源极/漏极区域和电耦合到源极/漏极区域的电极。 有源区在第一面处与栅极氧化膜接触，源/漏区的一部分位于第一面的上方。 电极在第二面处与源极/漏极区域接触，第二面部相对于第一面构成一个角度。

公开(公告)号：US5880500A

公开(公告)日：1999-03-09

申请号：US675595

申请日：1996-07-03

申请人： Hiroshi Iwata ,  Masayuki Nakano ,  Seizo Kakimoto

发明人： Hiroshi Iwata ,  Masayuki Nakano ,  Seizo Kakimoto

IPC分类号： H01L21/033 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/6659 ,  H01L21/0332 ,  H01L21/26586 ,  H01L21/28017 ,  H01L21/823807 ,  H01L27/0928 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833

摘要： A semiconductor device having a gate electrode on a Si-substrate through a gate oxide film; a first impurity diffusion region having a conductivity type reversed to a well which will form a part of source and drain regions in the two opposing sides of the gate electrode through gate electrode sidewall dielectric films; a second impurity diffusion region having the same conductivity type as the first impurity diffusion region beneath the gate electrode sidewall dielectric film, touching a channel region directly below the gate electrode and being shallower than the first impurity diffusion region; a titanium silicide film on the gate electrode and the surface of the Si-substrate of the first impurity diffusion region in the two opposing sides of the gate electrode sidewall dielectric film; and a third impurity diffusion region, formed in the first impurity diffusion region, having a higher concentration than the first impurity diffusion region and the same conductivity type as the first and second impurity diffusion region. The above semiconductor device is able to suppress the short-channel effects, and reduce the source-drain parasitic resistance and the source-drain junction leakage current while maintaining a small source-drain capacity.

摘要翻译： 一种通过栅极氧化膜在Si衬底上具有栅电极的半导体器件; 具有与阱相反的导电类型的第一杂质扩散区，其将通过栅电极侧壁电介质膜在栅电极的两个相对侧中形成源区和漏区的一部分; 第二杂质扩散区，与栅电极侧壁电介质膜下方的第一杂质扩散区具有相同的导电类型，与栅电极正下方的沟道区相比，比第一杂质扩散区浅; 所述栅极电极上的钛硅化物膜和所述栅电极侧壁电介质膜的两个相对侧中的所述第一杂质扩散区域的所述Si衬底的表面; 和形成在第一杂质扩散区中的第三杂质扩散区，其具有比第一杂质扩散区高的浓度和与第一和第二杂质扩散区相同的导电类型。 上述半导体器件能够抑制短沟道效应，并且在保持较小的源极 - 漏极容量的同时降低源极 - 漏极寄生电阻和源极 - 漏极结漏电流。

公开(公告)号：US07176526B2

公开(公告)日：2007-02-13

申请号：US10899183

申请日：2004-07-27

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A–A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106。 源极区域106和漏极区域106中的至少一个具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US06515340B2

公开(公告)日：2003-02-04

申请号：US09917954

申请日：2001-07-31

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/2257 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78654

摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.

公开(公告)号：US06426532B1

公开(公告)日：2002-07-30

申请号：US09720714

申请日：2001-04-19

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L31119

CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。

公开(公告)号：US5926741A

公开(公告)日：1999-07-20

申请号：US888470

申请日：1997-07-07

申请人： Toshimasa Matsuoka ,  Masayuki Nakano ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Toshimasa Matsuoka ,  Masayuki Nakano ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L21/31

CPC分类号： H01L21/28202 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/28211 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/518

摘要： In a method of forming gate dielectric films, a surface of a Si wafer is first cleaned in an inert gas ambient into a clean state having no naturally oxidized films. Then, after replacing the inert gas ambient with an oxidizing gas containing no nitrogen without exposing the wafer to air, the wafer is heated in the replaced ambient to form a first silicon oxide film on the silicon surface. Then, the ambient is again replaced with an oxidizing gas containing nitrogen, and the wafer is heated in the replaced ambient to form a first oxynitride film between the first silicon oxide film and the silicon. Thereafter, re-oxidation of the wafer is performed in an ambient of oxidizing gas containing no nitrogen to form a second silicon oxide film between the first oxynitride film and the silicon.

摘要翻译： 在形成栅极电介质膜的方法中，首先将Si晶片的表面在惰性气体环境中清洁成没有天然氧化膜的清洁状态。 然后，在用不含氮的氧化气体代替惰性气体环境而不将晶片暴露于空气之后，在更换的环境中加热晶片，以在硅表面上形成第一氧化硅膜。 然后，再次用含有氮的氧化气体代替环境，并且在更换的环境中加热晶片，以在第一氧化硅膜和硅之间形成第一氮氧化物膜。 此后，在不含氮的氧化气体的环境中进行晶片的再氧化，以在第一氮氧化物膜和硅之间形成第二氧化硅膜。