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公开(公告)号：US20050263811A1
公开(公告)日：2005-12-01
申请号：US11196267
申请日：2005-08-04
IPC分类号： G11C11/407 , G11C5/02 , G11C11/401 , G11C11/4097 , H01L21/8242 , H01L23/50 , H01L27/02 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memeory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side therof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.
摘要翻译： 提供了诸如DRAM和SDRAM n的大容量存储器，其中接合焊盘PS和PD不位于中心，而是位于配置在四层的上侧的存储阵列区域UL和UR之间的中心 存储体0至3的存储体结构以及位于下侧的存储器阵列区域DL和DR。 其次，接合焊盘PS和PD的布置在左右交错，使得右半边焊盘PD相对于左半键焊盘向上移动约30μm。 需要靠近存储器阵列区域DL和DR的读出放大器，列解码器和主放大器设置在接合焊盘PS和PD以及下部存储器阵列区域DL和DR之间，并且进一步间接地 外围电路设置在接合焊盘PS和PD的上侧。
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公开(公告)号：US20080265284A1
公开(公告)日：2008-10-30
申请号：US12146654
申请日：2008-06-26
IPC分类号： H01L27/10 , H01L27/108
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.
摘要翻译： 一种形成在半导体衬底上的半导体器件，包括形成在第一区域中并包括第一字线的第一存储器阵列，跨越第一字线的第一位线以及第一字线和第一位线的交叉处的存储器单元 第二存储器阵列，其形成在第二区域中，并且包括第二字线，跨越第二字线的第二位线，以及在第二字线和第二位线的交点处的存储单元，以及位于第三字线 区域，其中第一区域，第三区域和第二区域沿第一方向以该顺序排列，地址输入焊盘布置在基板的第一方向的中心轴线和第一区域之间，并且没有地址 输入垫布置在中心轴线和第二区域之间。
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公开(公告)号：US07400034B2
公开(公告)日：2008-07-15
申请号：US11196267
申请日：2005-08-04
IPC分类号： H01L23/52
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： There is provided a large capacity memory such as a DRAM and an SDRAM n which bonding pads PS and PD are not located at the center, but are displaced from the center between memory array regions UL and UR, disposed on the upper side of a four-bank structure of banks 0 through 3, and memory array regions DL and DR, disposed on the lower side thereof. Secondly, the disposition of the bonding pads PS and PD is staggered on the right and left such that the right half bonding pads PD are shifted up relative to the left half bonding pads by about 30 μm. Only a sense amplifier, a column decoder and a main amplifier, which need to be near to the memory array regions DL and DR, are disposed between the bonding pads PS and PD, and the lower memory array regions DL and DR, and further indirect peripheral circuits are disposed on the upper side of the bonding pads PS and PD.
摘要翻译： 提供了诸如DRAM和SDRAM n的大容量存储器，其中接合焊盘PS和PD不位于中心，而是位于设置在四个的上侧的存储器阵列区域UL和UR之间的中心 存储体0至3的存储体结构以及位于其下侧的存储器阵列区域DL和DR。 其次，接合焊盘PS和PD的布置在左右交错，使得右半边焊盘PD相对于左半键焊盘向上移动约30μm。 需要靠近存储器阵列区域DL和DR的读出放大器，列解码器和主放大器设置在接合焊盘PS和PD以及下部存储器阵列区域DL和DR之间，并且进一步间接地 外围电路设置在接合焊盘PS和PD的上侧。
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公开(公告)号：US07638871B2
公开(公告)日：2009-12-29
申请号：US12146654
申请日：2008-06-26
IPC分类号： H01L23/52
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C5/14 , G11C11/4097 , G11C2207/105 , H01L23/50 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/105 , H01L27/10897 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/45144 , H01L2224/48247 , H01L2224/49113 , H01L2224/49171 , H01L2224/49175 , H01L2924/01005 , H01L2924/01027 , H01L2924/01079 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device, formed on a semiconductor substrate, including a first memory array formed in a first region and including first word lines, first bit lines across the first word lines, and memory cells at intersections of the first word lines and the first bit lines, a second memory array which is formed in a second region and including second word lines, second bit lines across the second word lines, and memory cells at intersections of the second word lines and the second bit lines, and address pads located in a third region, in which the first region, the third region and the second region are arranged in that order in the first direction, the address input pads being arranged between a center axis of the first direction of the substrate and the first region, and no address input pads are arranged between the center axis and the second region.
摘要翻译： 一种形成在半导体衬底上的半导体器件，包括形成在第一区域中并包括第一字线的第一存储器阵列，跨越第一字线的第一位线以及第一字线和第一位线的交叉处的存储器单元 第二存储器阵列，其形成在第二区域中，并且包括第二字线，跨越第二字线的第二位线，以及在第二字线和第二位线的交点处的存储单元，以及位于第三字线 区域，其中第一区域，第三区域和第二区域沿第一方向以该顺序排列，地址输入焊盘布置在基板的第一方向的中心轴线和第一区域之间，并且没有地址 输入垫布置在中心轴线和第二区域之间。
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公开(公告)号：US4678161A
公开(公告)日：1987-07-07
申请号：US893448
申请日：1986-08-07
CPC分类号： F16K5/0626 , F16K27/067 , F16K5/201
摘要： A ball valve in which the ball of the valve is positively prevented from blowing out of the valve body in both directions, even if the valve is connected in the wrong direction or the fluid pressure is applied to the valve in the opposite direction. The ball is arranged in a valve body to selectively open and close a fluid passage in the body, and annular seals abut against the ball from both sides of the fluid passage, the annular seals being pushed towards the ball by seal carriers. In one embodiment, one of the seal carriers has a flange on the periphery of one end thereof, and the flange is locked to a step from inside which is formed on inner surface of one end portion of the valve body. In a second embodiment, the ball additionally has two grooves with abutting walls in respective ones of which a spindle and a pin coaxial with the spindle are fitted with the abutting walls positioned on the side of the one seal carrier.
摘要翻译： 即使阀以错误的方向连接或流体压力沿相反方向施加到阀，也可以将阀的球积极地防止两个方向从阀体吹出的球阀。 球体设置在阀体中以选择性地打开和关闭主体中的流体通道，并且环形密封件从流体通道的两侧抵靠球体，环形密封件被密封载体推向球体。 在一个实施例中，一个密封载体在其一端的周边上具有凸缘，并且凸缘被锁定在形成在阀体的一个端部的内表面上的内部的台阶上。 在第二实施例中，球还具有两个凹槽，其中相应的两个凹槽中的一个，其中主轴和与主轴同轴的销装配有位于一个密封载体侧面上的邻接壁。
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公开(公告)号：US5327937A
公开(公告)日：1994-07-12
申请号：US1729
申请日：1993-01-06
申请人： Shigenobu Kato , Yasuo Yamabe
发明人： Shigenobu Kato , Yasuo Yamabe
CPC分类号： F16K7/16 , Y10T137/87716
摘要： A branched valve includes a main flow passage and a branch flow passage provided in a main body, a weir provided between the main and branch flow passages, and a valve disc which can contact with and come off from the weir and which selectively connects and disconnects the main and branch flow passages, wherein a branch flow entrance wall of the branch flow passage integrated with the weir has either a flat surface or a convex surface. The outer wall of the branch flow exit of the main flow passage may rise vertically from the outer wall of the main flow passage, and the side wall of the weir is located approximately on the center line of the main flow passage. The branch flow passage may be provided so that the center line thereof is located higher than the center line of the main flow passage. The valve disc may be a diaphragm.
摘要翻译： 分流阀包括主流道和设置在主体中的分支流动通道，设置在主流道和分支流道之间的堰和可与堰接触和脱离的阀盘，并且其选择性地连接和断开 主流道和分支流道，其中与堰一体的分支流动通道的分支流入口壁具有平坦表面或凸面。 主流路的分支流出口的外壁可以从主流路的外壁垂直地上升，堰的侧壁大致位于主流路的中心线上。 分支流路可以设置成使其中心线位于比主流路的中心线高的位置。 阀盘可以是隔膜。
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公开(公告)号：US4384705A
公开(公告)日：1983-05-24
申请号：US311098
申请日：1981-10-13
申请人： Shigenobu Kato
发明人： Shigenobu Kato
摘要： A stop valve includes a main body which defines a fluid passage and a valve chamber. The stop valve further includes a spindle having one end connected to a handle and the other end inserted into said valve chamber, a valve seat positioned in said fluid passage and confronting said valve body, and a cap member positioned above said valve chamber. The outer end of the spindle is coupled rotatably to the valve body, while the rotation of the valve body is prevented by a rotation preventive means. A packing is interposed between the valve body and the valve chamber. The valve body is in sliding contact with said packing along the axial direction thereof during operation, upon rotation of the spindle about its axis.
摘要翻译： 截止阀包括限定流体通道的主体和阀室。 所述截止阀还包括主轴，其一端连接到手柄，另一端插入所述阀室，定位在所述流体通道中并面对所述阀体的阀座以及位于所述阀室上方的盖构件。 主轴的外端可旋转地联接到阀体，同时通过旋转防止装置防止阀体的旋转。 在阀体和阀室之间插入有填料。 当主轴绕其轴旋转时，阀体在操作期间沿其轴向方向与所述密封件滑动接触。
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