公开(公告)号：US06642148B1

公开(公告)日：2003-11-04

申请号：US10126326

申请日：2002-04-19

申请人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

发明人： Kouros Ghandehari ,  Emmanuil H. Lingunis ,  Mark S. Chang ,  Angela Hui ,  Scott Bell ,  Jusuke Ogura

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/743 ,  H01L27/112 ,  H01L27/11521 ,  H01L27/11568

摘要： The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

摘要翻译： 本发明一般涉及一种在半导体衬底内形成渐变结的方法。 在半导体衬底上形成第一掩模图案，其具有由第一横向尺寸表征的第一开口。 半导体衬底掺杂有第一掺杂剂，使用第一掩模图案作为掺杂掩模，由此在第一开口下面的半导体衬底中形成第一掺杂区域。 第一掩模图案被膨胀以将第一开口的第一横向尺寸减小到第二横向尺寸。 然后使用膨胀的第一掩模图案作为掺杂掩模，然后用半导体衬底掺杂第二掺杂剂，从而在半导体衬底中形成第二掺杂区，并且还限定半导体衬底内的渐变结。

公开(公告)号：US06809033B1

公开(公告)日：2004-10-26

申请号：US10045354

申请日：2001-11-07

申请人： Angela Hui ,  Jusuke Ogura

发明人： Angela Hui ,  Jusuke Ogura

IPC分类号： H01L21311

CPC分类号： H01L21/31116 ,  H01L21/32139

摘要： One aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device.

摘要翻译： 本发明的一个方面涉及从表面特别是硅表面去除硬掩模的方法。 通过首先施加牺牲涂层，然后等离子体蚀刻来去除硬掩模。 牺牲材料填充使用硬掩模形成的图案间隙，并在这些图案间隙内保护绝缘体，例如氧化物。 通过等离子体蚀刻与牺牲材料一起去除牺牲材料。 本发明提供了一种从硅层去除硬掩模的方法，而不会明显损害硅层或任何暴露的氧化物，并且可以应用于各种集成电路器件制造工艺中，例如对闪存器件的浮动栅极图案进行构图。

公开(公告)号：US20070262412A1

公开(公告)日：2007-11-15

申请号：US11781551

申请日：2007-07-23

申请人： Angela Hui ,  Jusuke Ogura ,  Yider Wu

发明人： Angela Hui ,  Jusuke Ogura ,  Yider Wu

IPC分类号： H01L29/00

CPC分类号： H01L21/76224

摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

摘要翻译： 一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。 可以在STI区域中蚀刻沟槽并填充绝缘材料。 抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。 可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。 可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。 可以将保护盖回蚀以暴露ARC层。 然而，保护盖仍然覆盖并保护绝缘材料。 通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。

公开(公告)号：US06713809B1

公开(公告)日：2004-03-30

申请号：US09809969

申请日：2001-03-16

申请人： Jusuke Ogura ,  Kazuhiro Kurihara ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

发明人： Jusuke Ogura ,  Kazuhiro Kurihara ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  G11C16/0458 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。

公开(公告)号：US06573140B1

公开(公告)日：2003-06-03

申请号：US09810155

申请日：2001-03-16

申请人： Jusuke Ogura ,  Kiyoshi Izumi ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

发明人： Jusuke Ogura ,  Kiyoshi Izumi ,  Masaru Yano ,  Hideki Komori ,  Tuan Pham ,  Angela Hui

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7887

摘要： The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) devices that employ charge trapping within a floating gate to indicate a 0 or 1 bit state. A memory device is provided, according to an aspect of the invention, comprising a floating gate transistor having dual polysilicon floating gates with an isolation opening between floating gates. Processes for making the memory device according to the invention are also disclosed.

摘要翻译： 本发明一般涉及半导体存储器件，更具体地说涉及在浮置栅极内采用电荷俘获来表示0或1位状态的多位闪存电可擦除可编程只读存储器（EEPROM）器件。 根据本发明的一个方面，提供一种存储器件，其包括具有双重多晶硅浮动栅极的浮动栅极晶体管，在浮置栅极之间具有隔离开口。 还公开了用于制造根据本发明的存储器件的工艺。

公开(公告)号：US20090215243A1

公开(公告)日：2009-08-27

申请号：US12369859

申请日：2009-02-12

申请人： Jusuke Ogura ,  Hikaru Kokura ,  Hideyuki Kojima ,  Toru Anezaki ,  Hiroyuki Ogawa ,  Junichi Ariyoshi

发明人： Jusuke Ogura ,  Hikaru Kokura ,  Hideyuki Kojima ,  Toru Anezaki ,  Hiroyuki Ogawa ,  Junichi Ariyoshi

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/823481 ,  H01L27/1052 ,  H01L27/11521

摘要： A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成限定有源区的隔离区，在半导体衬底上形成第一绝缘膜，形成第二绝缘膜，该第二绝缘膜具有与第一绝缘膜相同的蚀刻性能 绝缘膜，通过使用基于碳氟化合物的蚀刻气体的干蚀刻从有源区域和隔离区域上的第一区域选择性地去除第二绝缘膜，通过在第一绝缘膜上暴露于第一绝缘膜上形成的残留膜 含氧的气氛，通过湿式蚀刻从第一区域选择性地除去第一绝缘膜。

公开(公告)号：US06479411B1

公开(公告)日：2002-11-12

申请号：US09532347

申请日：2000-03-21

申请人： Angela T. Hui ,  Jusuke Ogura

发明人： Angela T. Hui ,  Jusuke Ogura

IPC分类号： H01L21311

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31662 ,  Y10S438/906 ,  Y10S438/942 ,  Y10S438/948

摘要： A method for forming high quality multiple thickness oxide layers having different thicknesses by eliminating descum induced defects. The method includes forming an oxide layer, masking the oxide layer with a photoresist layer, and developing the photoresist layer to expose at least one region of the oxide layer. The substrate is then heated and descummed to remove any residue resulting from developing the photoresist. Alternatively, the photoresist layer may be cured prior to heating and descumming the substrate. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

摘要翻译： 一种用于通过消除除去所引起的缺陷来形成具有不同厚度的高质量多层氧化物层的方法。 该方法包括形成氧化物层，用光致抗蚀剂层掩蔽氧化物层，以及显影光致抗蚀剂层以暴露氧化物层的至少一个区域。 然后将基材加热除去以除去由显影光致抗蚀剂产生的残留物。 或者，光致抗蚀剂层可以在加热和除去基板之前固化。 然后蚀刻氧化物层，并且在衬底上生长另一层氧化物之前剥离剩余的光致抗蚀剂。

公开(公告)号：US06461973B1

公开(公告)日：2002-10-08

申请号：US09535256

申请日：2000-03-23

申请人： Angela T. Hui ,  Jusuke Ogura

发明人： Angela T. Hui ,  Jusuke Ogura

IPC分类号： H01L21302

CPC分类号： H01L21/0206 ,  H01L21/28273 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31662 ,  H01L21/823462

摘要： A method for forming high quality oxide layers having different thicknesses by eliminating descum induced defects is disclosed. A semiconductor substrate is subjected to reactive ion etching. The semiconductor substrate includes a wafer, an oxide layer on the wafer, a developed photoresist mask on the oxide layer. The oxide layer is then etched, and the remaining photoresist is stripped before another layer of oxide is grown on the substrate.

公开(公告)号：US20100270623A1

公开(公告)日：2010-10-28

申请号：US12761516

申请日：2010-04-16

申请人： Tomoyuki Kirimura ,  Jusuke Ogura

发明人： Tomoyuki Kirimura ,  Jusuke Ogura

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823871 ,  H01L21/823807 ,  H01L29/7843

摘要： A semiconductor device fabrication method including: forming a gate conductor including a gate for a transistor in the first region, and a gate for a transistor in the second region, and a first film over a first stress film for covering the transistors; etching the first film from the second region by using a mask layer and etching the first film under the mask layer in the direction parallel to the surface of the semiconductor substrate by a first width from an edge of the first mask layer, and the first stress film from the second region; forming a second stress film covering the first stress film and the first film; etching the second stress film so that a portion of the second stress film overlaps a portion of the first stress film and a portion of the first film; and forming a contact hole connected with the gate conductor.

摘要翻译： 一种半导体器件制造方法，包括：形成包括第一区域中的晶体管的栅极和第二区域中的晶体管的栅极的栅极导体，以及用于覆盖晶体管的第一应力膜上的第一膜; 通过使用掩模层从所述第二区域蚀刻所述第一膜，并且在所述掩模层的下面沿着与所述半导体衬底的表面平行的方向从所述第一掩模层的边缘以第一宽度蚀刻所述第一膜，并且所述第一应力 第二区电影; 形成覆盖所述第一应力膜和所述第一膜的第二应力膜; 蚀刻第二应力膜，使得第二应力膜的一部分与第一应力膜的一部分和第一膜的一部分重叠; 并形成与栅极导体连接的接触孔。

公开(公告)号：US07265014B1

公开(公告)日：2007-09-04

申请号：US10799413

申请日：2004-03-12

申请人： Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

发明人： Angela T. Hui ,  Jusuke Ogura ,  Yider Wu

IPC分类号： H01L21/764 ,  H01L29/00

CPC分类号： H01L21/76224

摘要： A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

摘要翻译： 一种用于避免半导体器件的浅沟槽隔离（STI）区域中的氧化物气刨的方法和装置。 可以在STI区域中蚀刻沟槽并填充绝缘材料。 抗反射涂层（ARC）层可以沉积在STI区域上并延伸超出STI区域的边界。 可以蚀刻ARC层的一部分，留下ARC层的剩余部分超过STI区域并延伸超出STI区域的边界。 可以沉积保护盖以覆盖ARC层的剩余部分以及绝缘材料。 可以将保护盖回蚀以暴露ARC层。 然而，保护盖仍然覆盖并保护绝缘材料。 通过提供覆盖绝缘材料的保护帽，可以避免STI区域中的绝缘材料的气刨。