公开(公告)号：US6129091A

公开(公告)日：2000-10-10

申请号：US725804

申请日：1996-10-04

申请人： Kuei-Ying Lee ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Kuei-Ying Lee ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/00 ,  B08B3/08 ,  B08B3/12

CPC分类号： H01L21/67028

摘要： Current aqueous methods for removal of polymeric materials from the sidewalls of trenches etched into silicon wafers by reactive-ion-etching are inadequate for treating deep trenches having high aspect ratios. Spin-dry operations performed after the aqueous etching are incapable of completely removing rinse water and ionic species from these deep trenches, thereby leaving pockets of liquid. Subsequent evaporation of these pockets results in the concentration and eventual precipitation of residual ionic species creating watermarks. A two stage cleaning method is described in which the first stage dissolves the sidewall polymer and the second stage draws ionic species strongly chemisorbed onto the silicon surfaces into solution. A key feature of the method is that the wafer surface is not permitted to dry until after the final rinse.

摘要翻译： 目前的用于通过反应离子蚀刻从蚀刻到硅晶片的沟槽的侧壁上去除聚合材料的水性方法不足以处理具有高纵横比的深沟槽。 在水蚀刻之后执行的旋转干燥操作不能从这些深沟槽中完全去除漂洗水和离子物质，从而留下一些液体。 随后蒸发这些口袋导致产生水印的残留离子物质的浓度和最终沉淀。 描述了两阶段清洗方法，其中第一阶段溶解侧壁聚合物，第二阶段将离子物质强吸附在硅表面上成溶液。 该方法的一个关键特征是晶片表面不允许干燥直到最后冲洗。

公开(公告)号：US6015757A

公开(公告)日：2000-01-18

申请号：US887034

申请日：1997-07-02

申请人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/31056 ,  H01L21/31053 ,  H01L21/76229

摘要： A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nitride layer formed on a semiconductor wafer. A polysilicon layer is subsequently formed on the silicon nitride layer. A shallow trench is then created by photolithography and dry etching processes. The photoresist is subsequently removed in which an oxide layer is form in the shallow trench and on polysilicon layer for the purpose of isolation. A selective etching is used to etch the oxide layer. A CMP is performed to produce a planarized surface on a silicon wafer.

摘要翻译： 通过使用多晶硅层来防止形成在氮化硅层中的沟槽，公开了一种用于平坦化浅沟槽隔离的新方法。 本文所述的浅沟槽隔离件的形成包括形成在半导体晶片上的焊盘层和氮化硅层。 随后在氮化硅层上形成多晶硅层。 然后通过光刻和干蚀刻工艺创建浅沟槽。 随后去除光致抗蚀剂，其中在浅沟槽和多晶硅层上形成氧化物层，用于隔离的目的。 使用选择性蚀刻来蚀刻氧化物层。 执行CMP以在硅晶片上产生平坦化表面。

公开(公告)号：US5930644A

公开(公告)日：1999-07-27

申请号：US898791

申请日：1997-07-23

申请人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76224

摘要： A new method for planarizing a shallow trench isolation is disclosed by using a polysilicon layer or bottom anti-reflective coating (BARC) to form a reverse tone with a taper profile. The formation of the shallow trench isolation described includes a pad layer, and a silicon nitride layer formed-on a semiconductor wafer. Trenches are created by photolithography and dry etching processes. An oxide layer is formed in the trenches for the purpose of isolation. A polysilicon layer or bottom anti-reflective coating is subsequently formed on the oxide layer. A plurality of openings are generated in the polysilicon or the BARC layer. An etching is used to etch the oxide layer, thereby forming a reverse tone having a taper profile. A Chemical Mechanical Polishing is performed to planarize the surface of a semiconductor wafer.

摘要翻译： 通过使用多晶硅层或底部抗反射涂层（BARC）来公开用于平坦化浅沟槽隔离的新方法以形成具有锥形轮廓的反向色调。 所述的浅沟槽隔离体的形成包括在半导体晶片上形成的焊盘层和氮化硅层。 通过光刻和干蚀刻工艺产生沟槽。 为了隔离的目的，在沟槽中形成氧化物层。 随后在氧化物层上形成多晶硅层或底部抗反射涂层。 在多晶硅或BARC层中产生多个开口。 蚀刻用于蚀刻氧化物层，从而形成具有锥形轮廓的反向色调。 进行化学机械抛光以使半导体晶片的表面平坦化。

公开(公告)号：US06808985B1

公开(公告)日：2004-10-26

申请号：US10082021

申请日：2002-02-21

申请人： Kuei-Ying Lee ,  Shao-Yu Chou ,  Jiun-Nan Chen ,  Yue-Der Chih ,  Sam Sheng-Deh Chu ,  Feng-Ming Kuo

发明人： Kuei-Ying Lee ,  Shao-Yu Chou ,  Jiun-Nan Chen ,  Yue-Der Chih ,  Sam Sheng-Deh Chu ,  Feng-Ming Kuo

IPC分类号： H01L2100

CPC分类号： H01L27/11526 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11293 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11546

摘要： A method of fabricating ROM products through the use of embedded flash/EEPROM prototypes is disclosed. This is accomplished by first forming a Flash/EEPROM prototype, performing programming simulations on the prototype, developing a ROM code and mask, and then forming a ROM product in the same manufacturing line by skipping certain Flash/EEPROM steps and then implanting the ROM code into the final ROM product. The method improves turn-around-time in the manufacturing line, and reduces cost to the customer. A method of doing business is also disclosed directed to providing ROM products to a customer without much redesign time and effort on the part of the customer.

摘要翻译： 公开了通过使用嵌入式闪存/ EEPROM原型来制造ROM产品的方法。 这是通过首先形成闪存/ EEPROM原型，对原型进行编程仿真，开发ROM代码和掩码，然后通过跳过某些闪存/ EEPROM步骤在同一生产线上形成ROM产品，然后植入ROM代码 进入最终的ROM产品。 该方法提高了生产线的周转时间，降低了客户的成本。 还公开了一种开展业务的方法，其目的是向客户提供ROM产品，而不需要客户的重新设计时间和精力。

公开(公告)号：US06350662B1

公开(公告)日：2002-02-26

申请号：US09357244

申请日：1999-07-19

申请人： Kong-Beng Thei ,  Kuei-Ying Lee ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

发明人： Kong-Beng Thei ,  Kuei-Ying Lee ,  Dun-Nian Yaung ,  Shou-Gwo Wuu

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method to form shallow trench isolations with reduced substrate defects by using a nitrogen anneal is achieved. A silicon substrate is provided. The silicon substrate is etched where not protected by a photoresist mask to form shallow trenches where shallow trench isolations are planned. A liner oxide layer is grown on the interior surfaces of the shallow trenches. The silicon substrate and the liner oxide layer are annealed to reduce or eliminate defects, dislocations, interface traps, and stress in the silicon substrate. An isolation oxide layer is deposited overlying the liner oxide layer and completely filling the shallow trenches. The isolation oxide layer is etched down to the top surface of the silicon substrate and thereby forms the shallow trench isolations. The integrated circuit device is completed.

摘要翻译： 实现了通过使用氮退火形成具有减少的衬底缺陷的浅沟槽隔离的方法。 提供硅衬底。 蚀刻硅衬底，其中未被光致抗蚀剂掩模保护以形成浅沟槽，其中规划浅沟槽隔离。 在浅沟槽的内表面上生长衬里氧化物层。 对硅衬底和衬里氧化物层进行退火以减少或消除硅衬底中的缺陷，位错，界面陷阱和应力。 隔离氧化物层沉积在衬垫氧化物层上并且完全填充浅沟槽。 隔离氧化物层被蚀刻到硅衬底的顶表面，从而形成浅沟槽隔离。 集成电路装置完成。

公开(公告)号：US06110793A

公开(公告)日：2000-08-29

申请号：US104033

申请日：1998-06-24

申请人： Kuei-Ying Lee ,  Kong-Beng Thei ,  Bou-Fun Chen

发明人： Kuei-Ying Lee ,  Kong-Beng Thei ,  Bou-Fun Chen

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76235

摘要： A method for forming an improved trench isolation having a conformal liner oxide and rounded top and bottom corners in the trench was achieved. The conformal liner oxide improves the CVD gap-filling capabilities for these deep submicron wide trenches, and the rounded corners improve the electrical characteristics of the devices in the adjacent device areas. After etching trenches with vertical sidewalls in the silicon substrate, a two-step oxidation process is used to form the conformal liner oxide. A first oxidation step using a low-oxygen flow rate and a low temperature (about 850 to 920.degree. C.) is used to achieve rounded bottom corners. A second oxidation step at a low-oxygen flow rate and a higher temperature (about 1000 to 1150.degree. C.) is used to achieve rounded top corners. The two-step process also results in a more conformal liner oxide. The trenches are then filled with a CVD oxide and polished or etched back to an oxidation-barrier layer/etch-stop layer over the device areas to complete the trench isolation.

摘要翻译： 实现了在沟槽中形成具有共形衬垫氧化物和圆形顶部和底部角的改进的沟槽隔离的方法。 保形衬垫氧化物改善了这些深亚微米宽沟槽的CVD间隙填充能力，并且圆角提高了相邻器件区域中器件的电气特性。 在硅衬底中用垂直侧壁蚀刻沟槽之后，使用两步氧化工艺来形成保形衬里氧化物。 使用低氧气流速度和低温（约850-920℃）的第一氧化步骤来实现圆角的底角。 使用低氧流速和较高温度（约1000至1150℃）的第二氧化步骤来实现圆角顶角。 两步法也导致更适形的衬里氧化物。 然后用CVD氧化物填充沟槽并在器件区域上抛光或蚀刻回到氧化阻挡层/蚀刻停止层以完成沟槽隔离。

公开(公告)号：US06214698B1

公开(公告)日：2001-04-10

申请号：US09480270

申请日：2000-01-11

申请人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Kuei-Ying Lee ,  Chu-Yun Fu ,  Kong-Beng Thei

发明人： Jhon-Jhy Liaw ,  Jin-Yuan Lee ,  Kuei-Ying Lee ,  Chu-Yun Fu ,  Kong-Beng Thei

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for filling a trench within a substrate. First a substrate is provided having a trench formed therein. The trench has a bottom surface and opposing side walls. An undoped silicon glass liner is then thermally grown to coat the bottom surface and side walls of the trench. An undoped silicon oxide layer is then deposited over the undoped silicon glass liner. A boron doped silicon oxide layer is then deposited over the undoped silicon oxide layer, filling the trench. The boron doped silicon oxide layer is then heated to reflow the boron doped silicon oxide to fill any void initially formed within the boron doped silicon oxide layer within the trench, thereby eliminating any void so formed.

摘要翻译： 一种填充衬底内的沟槽的方法。 首先，提供具有形成在其中的沟槽的衬底。 沟槽具有底面和相对的侧壁。 然后将未掺杂的硅玻璃衬里热生长以涂覆沟槽的底表面和侧壁。 然后将未掺杂的氧化硅层沉积在未掺杂的硅玻璃衬垫上。 然后将硼掺杂的氧化硅层沉积在未掺杂的氧化硅层上，填充沟槽。 然后加热硼掺杂的氧化硅层以回流硼掺杂的氧化硅以填充初始形成在沟槽内的硼掺杂的氧化硅层内的任何空隙，从而消除如此形成的任何空隙。

公开(公告)号：US6046062A

公开(公告)日：2000-04-04

申请号：US373246

申请日：1999-08-12

申请人： Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

发明人： Kuo-Ching Huang ,  Chuan-Jane Chao ,  Kuei-Ying Lee ,  Yean-Kuen Fang

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/14

摘要： This invention relates to the characterization of integrated circuit devices and more particularly to an improved method for monitoring for unacceptable kink behavior, in the threshold voltage characteristics of FET devices, that can be caused by a tendency for reduced gate oxide thickness and reduced substrate doping concentration, along the length of channel regions bounded by STI. This is achieved by comparing a pair of drain current versus gate voltage characteristics, as a function of two values of substrate voltage. Relative voltage shifts between the two curves are compared at a value of drain current that is well below the kink and at a value of drain current that is well above the kink. The quantitative degree of kink behavior is determined by how much greater the voltage shift, corresponding to the value of drain current well above the kink, exceeds the voltage shift, corresponding to the value of drain current well below the kink.

摘要翻译： 本发明涉及集成电路器件的特性，更具体地说，涉及一种用于在FET器件的阈值电压特性中监测不可接受的扭结行为的改进方法，这可能是由于栅极氧化物厚度减小和衬底掺杂浓度降低引起的 沿着由STI界定的频道区域的长度。 这是通过将一对漏极电流与栅极电压特性作为衬底电压的两个值的函数来实现的。 在两个曲线之间的相对电压偏移在远低于扭结的漏极电流的值处以及远远高于扭结的漏极电流的值进行比较。 扭结行为的定量程度由对应于远低于扭结的漏极电流值的电压偏移量超过相应于低于扭结线圈的漏极电流的值的电压偏移量来确定多大。

公开(公告)号：US5521119A

公开(公告)日：1996-05-28

申请号：US274417

申请日：1994-07-13

申请人： Shu-Hui Chen ,  Kuei-Ying Lee ,  Cheng-Yeh Shih ,  Wing-Lang Zang

发明人： Shu-Hui Chen ,  Kuei-Ying Lee ,  Cheng-Yeh Shih ,  Wing-Lang Zang

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76877 ,  H01L21/76838

摘要： A new method of metallization without unwanted precipitates using a tungsten plug is achieved. Semiconductor device structures are formed in and on a semiconductor substrate. A contact hole is opened through an insulating layer to the semiconductor substrate. A glue layer is deposited conformally over the surface of the insulating layer and within the contact opening. A layer of tungsten is blanket deposited over the glue layer. The tungsten layer is etched back leaving the tungsten only within the contact opening to form a tungsten plug. The etching back leaves impurities on the surface of the glue layer. Those impurities will react with water or air to form precipitates. The precipitates are removed using a wet chemical etch. The substrate is post treated with argon ion sputtering to prevent future formation of precipitates. A second metal layer is deposited over the tungsten plug and the glue layer to complete the tungsten plug metallization without unwanted precipitates in the fabrication of an integrated circuit.

摘要翻译： 实现了使用钨丝塞不需要沉淀的金属化的新方法。 在半导体衬底中形成半导体器件结构。 接触孔通过绝缘层向半导体衬底开口。 粘合剂层保形地沉积在绝缘层的表面上并且在接触开口内。 一层钨被覆盖在胶层上。 钨层被回蚀，仅在接触孔内留下钨以形成钨丝塞。 蚀刻后在胶层表面留下杂质。 这些杂质将与水或空气反应形成析出物。 使用湿法化学蚀刻除去沉淀物。 用氩离子溅射对衬底进行后处理，以防止未来形成析出物。 第二金属层沉积在钨插塞和胶层上，以在集成电路的制造中完成钨插塞金属化而不需要沉淀。