公开(公告)号：US6129091A

公开(公告)日：2000-10-10

申请号：US725804

申请日：1996-10-04

申请人： Kuei-Ying Lee ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Kuei-Ying Lee ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/00 ,  B08B3/08 ,  B08B3/12

CPC分类号： H01L21/67028

摘要： Current aqueous methods for removal of polymeric materials from the sidewalls of trenches etched into silicon wafers by reactive-ion-etching are inadequate for treating deep trenches having high aspect ratios. Spin-dry operations performed after the aqueous etching are incapable of completely removing rinse water and ionic species from these deep trenches, thereby leaving pockets of liquid. Subsequent evaporation of these pockets results in the concentration and eventual precipitation of residual ionic species creating watermarks. A two stage cleaning method is described in which the first stage dissolves the sidewall polymer and the second stage draws ionic species strongly chemisorbed onto the silicon surfaces into solution. A key feature of the method is that the wafer surface is not permitted to dry until after the final rinse.

摘要翻译： 目前的用于通过反应离子蚀刻从蚀刻到硅晶片的沟槽的侧壁上去除聚合材料的水性方法不足以处理具有高纵横比的深沟槽。 在水蚀刻之后执行的旋转干燥操作不能从这些深沟槽中完全去除漂洗水和离子物质，从而留下一些液体。 随后蒸发这些口袋导致产生水印的残留离子物质的浓度和最终沉淀。 描述了两阶段清洗方法，其中第一阶段溶解侧壁聚合物，第二阶段将离子物质强吸附在硅表面上成溶液。 该方法的一个关键特征是晶片表面不允许干燥直到最后冲洗。

公开(公告)号：US6015757A

公开(公告)日：2000-01-18

申请号：US887034

申请日：1997-07-02

申请人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/31056 ,  H01L21/31053 ,  H01L21/76229

摘要： A new method for planarization of shallow trench isolation is disclosed by using a polysilicon layer to prevent trench formed in a silicon nitride layer. The formation of the shallow trench isolation described herein includes a pad layer and a silicon nitride layer formed on a semiconductor wafer. A polysilicon layer is subsequently formed on the silicon nitride layer. A shallow trench is then created by photolithography and dry etching processes. The photoresist is subsequently removed in which an oxide layer is form in the shallow trench and on polysilicon layer for the purpose of isolation. A selective etching is used to etch the oxide layer. A CMP is performed to produce a planarized surface on a silicon wafer.

摘要翻译： 通过使用多晶硅层来防止形成在氮化硅层中的沟槽，公开了一种用于平坦化浅沟槽隔离的新方法。 本文所述的浅沟槽隔离件的形成包括形成在半导体晶片上的焊盘层和氮化硅层。 随后在氮化硅层上形成多晶硅层。 然后通过光刻和干蚀刻工艺创建浅沟槽。 随后去除光致抗蚀剂，其中在浅沟槽和多晶硅层上形成氧化物层，用于隔离的目的。 使用选择性蚀刻来蚀刻氧化物层。 执行CMP以在硅晶片上产生平坦化表面。

公开(公告)号：US5930644A

公开(公告)日：1999-07-27

申请号：US898791

申请日：1997-07-23

申请人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Kuei-Ying Lee ,  Hun-Jan Tao

IPC分类号： H01L21/3105 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/31053 ,  H01L21/76224

摘要： A new method for planarizing a shallow trench isolation is disclosed by using a polysilicon layer or bottom anti-reflective coating (BARC) to form a reverse tone with a taper profile. The formation of the shallow trench isolation described includes a pad layer, and a silicon nitride layer formed-on a semiconductor wafer. Trenches are created by photolithography and dry etching processes. An oxide layer is formed in the trenches for the purpose of isolation. A polysilicon layer or bottom anti-reflective coating is subsequently formed on the oxide layer. A plurality of openings are generated in the polysilicon or the BARC layer. An etching is used to etch the oxide layer, thereby forming a reverse tone having a taper profile. A Chemical Mechanical Polishing is performed to planarize the surface of a semiconductor wafer.

摘要翻译： 通过使用多晶硅层或底部抗反射涂层（BARC）来公开用于平坦化浅沟槽隔离的新方法以形成具有锥形轮廓的反向色调。 所述的浅沟槽隔离体的形成包括在半导体晶片上形成的焊盘层和氮化硅层。 通过光刻和干蚀刻工艺产生沟槽。 为了隔离的目的，在沟槽中形成氧化物层。 随后在氧化物层上形成多晶硅层或底部抗反射涂层。 在多晶硅或BARC层中产生多个开口。 蚀刻用于蚀刻氧化物层，从而形成具有锥形轮廓的反向色调。 进行化学机械抛光以使半导体晶片的表面平坦化。

公开(公告)号：US06326296B1

公开(公告)日：2001-12-04

申请号：US09108867

申请日：1998-07-01

申请人： Chia Shiung Tsai ,  Hun-Jan Tao

发明人： Chia Shiung Tsai ,  Hun-Jan Tao

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3185 ,  H01L2221/1036

摘要： A new method of forming a dual damascene interconnect is disclosed for manufacturing semiconductor substrates. A contact/via hole is first formed in a first dielectric layer formed over a substructure of a substrate having devices formed therein and/or metal layers formed thereon. The contact/via hole is filled with a protective material prior to forming a second dielectric layer. Conductive line opening is formed in the second dielectric layer and over the contact/via hole having the protective material in it. The protective material protects the edge of the contact/via hole from damage due to the second etching of the conductive line opening. Thus, a dual damascene structure is disclosed wherein the integrity of the edge of the contact/via hole is preserved, avoiding any reliability problems in the semiconductor product.

摘要翻译： 公开了一种形成双镶嵌互连的新方法，用于制造半导体衬底。 接触/通孔首先形成在形成在其上形成有器件和/或其上形成金属层的衬底的子结构之上的第一电介质层中。 在形成第二电介质层之前，接触/通孔填充有保护材料。 导电线路开口形成在第二电介质层中并且在其中具有保护材料的接触/通孔之上。 保护材料保护接触/通孔的边缘免受由于导电线开口的第二次蚀刻的损害。 因此，公开了一种双镶嵌结构，其中保留了接触/通孔的边缘的完整性，避免了半导体产品中的任何可靠性问题。

公开(公告)号：US6040248A

公开(公告)日：2000-03-21

申请号：US104032

申请日：1998-06-24

申请人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Chao-Cheng Chen ,  Ming-Hsin Huang ,  Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/768 ,  H01L21/302 ,  C23F1/02 ,  H01L21/461

CPC分类号： H01L21/31138 ,  H01L21/76802

摘要： A process for plasma etching of contact and via openings in low-k organic polymer dielectric layers is described which overcomes problems of sidewall bowing and hardmask pattern deterioration by etching the organic layer in a high density plasma etcher with a chlorine/inert gas plasma. By adding chlorine to the oxygen/inert gas plasma, the development of an angular aspect or faceting of the hardmask pattern edges by ion bombardment is abated. Essentially vertical sidewalls are obtained in the openings etched in the organic polymer layer while hardmask pattern integrity is maintained. The addition of a passivating agent such as nitrogen, BCl.sub.3, or CHF.sub.3 to the etchant gas mixture further improves the sidewall profile by reducing bowing through protective polymer formation.

摘要翻译： 描述了一种用于等离子体蚀刻低k有机聚合物介电层中的接触和通孔开口的方法，其通过用氯/惰性气体等离子体在高密度等离子体蚀刻机中蚀刻有机层来克服侧壁弯曲和硬掩模图案劣化的问题。 通过向氧/惰性气体等离子体中加入氯，减少了通过离子轰击形成硬掩模图案边缘的角度方面或刻面。 在保持硬掩模图案完整性的同时，在有机聚合物层中蚀刻的开口中获得基本垂直的侧壁。 钝化剂如氮气，BCl3或CHF3添加到蚀刻剂气体混合物中，通过减少通过保护性聚合物形成的弯曲来进一步改善侧壁轮廓。

公开(公告)号：US06472335B1

公开(公告)日：2002-10-29

申请号：US09175019

申请日：1998-10-19

申请人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

发明人： Chia-Shiung Tsai ,  Yao-Yi Cheng ,  Hun-Jan Tao

IPC分类号： H01L2131

CPC分类号： H01L21/0214 ,  H01L21/02118 ,  H01L21/022 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/31629 ,  H01L21/3185 ,  H01L21/76801 ,  Y10S438/906 ,  Y10S438/958 ,  Y10S438/964

摘要： The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

摘要翻译： 本发明提供一种通过在形成上覆低K层之前进行HF浸渍蚀刻来处理氧化物，氮化硅或氮氧化硅绝缘层的表面来改善金属间电介质（IMD）层之间的粘合力的方法。 本发明提供了一种在氧化物，氮氧化硅（SiON）或氮化物IMD层14上制备低K IMD层20的方法，其具有改善的粘合性。 首先，在衬底上形成第一金属间介电层（IMD）层14。 接下来，在第一IMD层14上进行本发明的新型HF浸渍蚀刻以形成处理表面16.接下来，在第一IMD层14的粗糙表面16上形成由低K材料构成的第二BMD层。 经处理的表面16改善了第一IMD层氧化物（氧化物，SiN或SiON）和低k层之间的粘合性。 随后的光刻胶条步骤不会导致第一IMI层14和第二IMD层20（低K电介质）剥离。

公开(公告)号：US6165881A

公开(公告)日：2000-12-26

申请号：US177185

申请日：1998-10-23

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/665 ,  H01L21/0276 ,  H01L21/31116

摘要： I A method is achieved for removing a hardmask from a feature on a semiconductor wafer. The method comprises the following phases: depositing a buffer layer overall; etching back the buffer layer in an etching apparatus to expose the hardmask; etching the hardmask in the etching apparatus; and etching of the remaining buffer layer in the etching apparatus.

摘要翻译： I实现了从半导体晶片上的特征去除硬掩模的方法。 该方法包括以下阶段：整体沉积缓冲层; 在蚀刻装置中蚀刻缓冲层以暴露硬掩模; 在蚀刻装置中蚀刻硬掩模; 并蚀刻在蚀刻装置中的剩余缓冲层。

公开(公告)号：US6037266A

公开(公告)日：2000-03-14

申请号：US161567

申请日：1998-09-28

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai

IPC分类号： H01L21/3213 ,  H01L21/00

CPC分类号： H01L21/32137

摘要： A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O.sub.2 gasses, and applying a first TCP Power and a first Bias power;b) in STEP 2, etching the hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power;c) in STEP 3--stripping the bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power;d) in STEP 4--etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.

摘要翻译： 使用新的4步蚀刻工艺使用氧化物硬掩模图案化多晶硅栅极的方法。 所有4个蚀刻步骤都在多晶硅高密度等离子体（TCP-变压器耦合等离子体）蚀刻器中进行。 形成多层半导体结构35（图1），包括：基板10，栅极氧化物层14，多晶硅层18，硬掩模层22和底部抗反射涂层（BARC）层26和 4步蚀刻工艺包括：a）在步骤1中，通过流过HBr和O2气体并施加第一TCP功率和第一偏压功率蚀刻底部抗反射涂层（BARC）层; b）在步骤2中，通过流动氟碳化物气体来蚀刻硬掩模; 以及施加第二TCP功率和第二偏置功率; c）在步骤3中 - 通过流动氧气并施加第三TCP功率和第三偏压功率来剥离底部抗反射涂层（BARC）层; d）在步骤4中，通过流动氯物质，氧物种蚀刻多晶硅层; 氦物种和溴气物种，并应用第四个TCP电源和第四个偏置电源。

公开(公告)号：US6015735A

公开(公告)日：2000-01-18

申请号：US6509

申请日：1998-01-13

申请人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

发明人： Shau-Lin Shue ,  Hun-Jan Tao ,  Chia-Shiung Tsai ,  Jenn-Ming Huang

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/302

CPC分类号： H01L27/1085 ,  H01L28/86

摘要： The present invention discloses a method for forming a DRAM capacitor that has improved charge storage capacity by utilizing a deposition process wherein alternating layers of doped and undoped dielectric materials are first deposited, a deep UV type photoresist layer is then deposited on top of the oxide layers such that during a high density plasma etching process for the cell opening, acidic reaction product is generated by the photoresist layer when exposed to UV emission in an etch chamber such that the sidewall of the cell opening is etched laterally in an uneven manner, i.e., the doped dielectric layer being etched more severely than the undoped dielectric layer thus forming additional surface area and an improved charge storage capacity for the capacitor formed.

摘要翻译： 本发明公开了一种用于形成DRAM电容器的方法，该DRAM电容器通过利用首先沉积掺杂和未掺杂电介质材料的交替层的沉积工艺具有改善的电荷存储容量，然后将深UV型光致抗蚀剂层沉积在氧化物层的顶部 使得在用于电池开口的高密度等离子体蚀刻工艺期间，当在蚀刻室中暴露于UV发射时，光致抗蚀剂层产生酸性反应产物，使得电池开口的侧壁以不均匀的方式横向蚀刻，即， 掺杂的介电层比非掺杂的介电层更严格地被蚀刻，从而形成额外的表面积和改善的形成的电容器的电荷存储容量。

公开(公告)号：US06620631B1

公开(公告)日：2003-09-16

申请号：US09573807

申请日：2000-05-18

申请人： Hun-Jan Tao ,  Chia-Shiung Tsai ,  Anthony Yen

发明人： Hun-Jan Tao ,  Chia-Shiung Tsai ,  Anthony Yen

IPC分类号： H01L21302

CPC分类号： H01L22/20 ,  H01J37/32935

摘要： Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a blanket target layer. There is then formed over the blanket target layer a patterned mask layer. There is then measured, while employing an optical method, a linewidth of the patterned mask layer to determine a patterned mask layer measured linewidth. There is then determined a deviation of the patterned mask layer measured linewidth from a patterned mask layer target linewidth. There is then etched, while employing a plasma etch method, the blanket target layer to form a patterned target layer while employing the patterned mask layer as a etch mask layer. Within the method, in conjunction the deviation of the patterned mask layer measured linewidth from the patterned mask layer target linewidth there is adjusted within the plasma etch method at least one plasma etch parameter such that a patterned target layer measured linewidth more closely approximates a patterned target layer target linewidth. Similarly, within the method, the measuring of the patterned mask layer measured linewidth while employing the optical method and the adjusting within the plasma etch method of the at least one plasma etch parameter are undertaken in-situ for each substrate within a series of substrates fabricated while employing the plasma etch method. Within a second embodiment of the present invention a blanket target layer thickness is measured while employing an optical method rather than a patterned masking layer linewidth.

摘要翻译： 在微电子制造的制造方法中，首先提供基板。 然后在衬底上形成覆盖目标层。 然后在毯状目标层上形成图案化的掩模层。 然后在采用光学方法时，测量图案化掩模层的线宽以确定图案化掩模层测量的线宽。 然后确定图案化掩模层测量的线宽与图案化掩模层目标线宽的偏差。 然后在采用等离子体蚀刻方法的同时蚀刻该覆盖层目标层以形成图案化目标层，同时采用图案化掩模层作为蚀刻掩模层。 在该方法中，结合图案化掩模层测量的线宽与图案化掩模层目标线宽的偏差，在等离子体蚀刻方法内调节至少一个等离子体蚀刻参数，使得图案化目标层测量的线宽更接近于图案化靶 层目标线宽。 类似地，在该方法中，在使用光学方法的同时测量线状图案测量线性以及等离子体蚀刻方法内的至少一种等离子体蚀刻参数的调整是在一系列衬底内的每个衬底的原位进行的 同时采用等离子体蚀刻方法。 在本发明的第二实施例中，使用光学方法而不是图案化掩蔽层线宽来测量覆盖目标层厚度。