公开(公告)号：US08598643B2

公开(公告)日：2013-12-03

申请号：US13235425

申请日：2011-09-18

申请人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Kaori Kawasaki ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US20120241846A1

公开(公告)日：2012-09-27

申请号：US13235425

申请日：2011-09-18

申请人： Kaori KAWASAKI ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Kaori KAWASAKI ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Takeshi Imamura ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一导电层，第二导电层，第一电极间绝缘膜和堆叠在第一导电层上方的第三导电层，存储膜，半导体层， 绝缘构件和硅化物层。 存储膜和半导体层形成在设置在第二导电层，第一电极间绝缘膜和第三导电层中的通孔的内表面上。 绝缘构件埋设在分割第二导电层，第一电极间绝缘膜和第三导电层的狭缝中。 硅化物层形成在狭缝中的第二导电层和第三导电层的表面上。 沿着狭缝的内表面，第二导电层和第三导电层之间的距离比层叠方向长。

公开(公告)号：US20120026775A1

公开(公告)日：2012-02-02

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C17/12

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US20120132981A1

公开(公告)日：2012-05-31

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US09064975B2

公开(公告)日：2015-06-23

申请号：US13409652

申请日：2012-03-01

申请人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Hideaki Aochi

IPC分类号： H01L29/765 ,  H01L21/84 ,  H01L27/10 ,  H01L27/115 ,  H01L27/12 ,  G11C19/00

CPC分类号： H01L21/84 ,  G11C19/00 ,  H01L27/10 ,  H01L27/11517 ,  H01L27/1203

摘要： In one embodiment, a shift register memory includes first and second control electrodes extending in a first direction parallel to a surface of a substrate, and facing each other in a second direction perpendicular to the first direction. The memory further includes a plurality of first floating electrodes provided in a line on a first control electrode side between the first and second control electrodes. The memory further includes a plurality of second floating electrodes provided in a line on a second control electrode side between the first and second control electrodes. Each of the first and second floating electrodes has a planar shape which is mirror-asymmetric with respect to a plane perpendicular to the first direction.

摘要翻译： 在一个实施例中，移位寄存器存储器包括在平行于衬底表面的第一方向上延伸的第一和第二控制电极，并且在垂直于第一方向的第二方向上彼此面对。 存储器还包括设置在第一和第二控制电极之间的第一控制电极侧的一行中的多个第一浮置电极。 存储器还包括设置在第一和第二控制电极之间的第二控制电极侧的一行中的多个第二浮置电极。 第一和第二浮动电极中的每一个具有相对于垂直于第一方向的平面镜像不对称的平面形状。

公开(公告)号：US09025377B2

公开(公告)日：2015-05-05

申请号：US13052195

申请日：2011-03-21

申请人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

发明人： Kunihiro Yamada ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Yoshiaki Fukuzumi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Kaori Kawasaki

IPC分类号： G11C16/22 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/22 ,  H01L27/11578 ,  H01L27/11582

摘要： According to one embodiment, a method of operating a semiconductor memory device is disclosed. The method can include storing read-only data in at least one selected from a memory cell of an uppermost layer and a memory cell of a lowermost layer of a plurality of memory cells connected in series via a channel body. The channel body extends upward from a substrate to intersect a plurality of electrode layers stacked on the substrate. The method can include prohibiting a data erase operation of the read-only memory cell having the read-only data stored in the read-only memory cell.

摘要翻译： 根据一个实施例，公开了一种操作半导体存储器件的方法。 该方法可以包括将至少一个从通过主体连接的多个存储单元的最上层的存储单元和最下层的存储单元中选出的至少一个存储在只读数据中。 通道体从衬底向上延伸以与堆叠在衬底上的多个电极层交叉。 该方法可以包括禁止具有存储在只读存储器单元中的只读数据的只读存储器单元的数据擦除操作。

公开(公告)号：US08766351B2

公开(公告)日：2014-07-01

申请号：US13112345

申请日：2011-05-20

申请人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

发明人： Takeshi Imamura ,  Yoshiaki Fukuzumi ,  Hideaki Aochi ,  Masaru Kito ,  Tomoko Fujiwara ,  Kaori Kawasaki ,  Ryouhei Kirisawa

IPC分类号： H01L29/788

CPC分类号： H01L27/11556 ,  H01L29/42324 ,  H01L29/7889

摘要： According to one embodiment, a columnar semiconductor, a floating gate electrode formed on a side surface of the columnar semiconductor via a tunnel dielectric film, and a control gate electrode formed to surround the floating gate electrode via a block dielectric film are provided.

摘要翻译： 根据一个实施例，提供了柱状半导体，通过隧道电介质膜形成在柱状半导体的侧表面上的浮栅电极和通过块状电介质膜包围浮置栅电极的控制栅电极。

公开(公告)号：US08218358B2

公开(公告)日：2012-07-10

申请号：US12851054

申请日：2010-08-05

申请人： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C11/14

CPC分类号： H01L27/11578 ,  G11C16/0466 ,  G11C16/06 ,  H01L27/11565 ,  H01L27/11582

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，堆叠体，半导体柱，电荷存储膜和驱动电路。 层叠体设置在基板上。 层叠体包括交替层叠有多个电极膜的多个绝缘膜。 在堆叠体中形成通孔，以在堆叠方向上对齐。 半导体柱被埋在通孔的内部。 电荷存储膜设置在电极膜和半导体柱之间。 驱动电路为电极膜提供电位。 通孔的直径与层叠方向的位置不同。 当穿透电极膜的通孔的直径减小时，驱动电路提供降低与半导体柱的电位差的电位。

公开(公告)号：US08178919B2

公开(公告)日：2012-05-15

申请号：US12727830

申请日：2010-03-19

申请人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoko Fujiwara ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L21/00

CPC分类号： H01L27/11551 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11556

摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.

摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。 连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

公开(公告)号：US20110031550A1

公开(公告)日：2011-02-10

申请号：US12727712

申请日：2010-03-19

申请人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件包括：堆叠结构单元，包括多个电极膜和沿第一方向交替堆叠的多个电极间绝缘膜; 第一选择栅电极，沿第一方向堆叠在层叠结构单元上; 第一半导体柱在第一方向上穿透层叠结构单元和第一选择栅电极; 设置在每个电极膜和第一半导体柱的交点处的第一存储单元; 以及设置在所述第一半导体柱和所述第一选择栅极之间的第一选择栅极绝缘膜，所述第一选择栅电极包括设置在所述第一选择栅电极的与所述第一方向垂直的面上的第一硅化物层。