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1.发明授权Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) 有权制造用于动态随机存取存储器（DRAM）的双缸电容器结构的方法公开(公告)号：US06403416B1
公开(公告)日：2002-06-11
申请号：US09226279
申请日：1999-01-07
IPC分类号： H01L218242
CPC分类号： H01L28/91
摘要： A method using a single masking step for making double-cylinder stacked capacitors for DRAMs which increases capacitance while eliminating erosion of an underlying oxide insulating layer when the masking step is misaligned is described. A planar silicon oxide (SiO2) first insulating layer is formed over device areas, and a first silicon nitride (Si3N4) etch-stop layer is deposited, and openings are etched for capacitor node contacts. A first polysilicon layer is deposited to a thickness sufficient to fill the openings and to form an essentially planar surface. A second insulating layer is deposited and patterned to form portions with vertical sidewalls over the node contacts. A conformal second Si3N4 layer is deposited and etched back to form spacers on the vertical sidewalls, and the first polysilicon layer is etched to the first Si3N4 layer. The second insulating layer is selectively removed using HF acid while the first polysilicon and first Si3N4 layers prevent etching of the underlying first SiO2 layer. A second polysilicon layer is deposited and etched back to form double-cylinder sidewalls for the capacitor bottom electrodes. The first and second Si3N4 layers are removed in hot phosphoric acid. The capacitors are completed by forming an interelectrode dielectric layer on the bottom electrodes, and depositing a third polysilicon layer for top electrodes.
摘要翻译： 描述了一种使用单个掩模步骤来制造用于DRAM的双圆柱体堆叠电容器的方法，其在掩蔽步骤未对准时消除了下面的氧化物绝缘层的侵蚀，同时增加了电容。 在器件区域上形成平面氧化硅（SiO 2）第一绝缘层，并沉积第一氮化硅（Si 3 N 4）蚀刻停止层，并且蚀刻用于电容器节点接触的开口。 第一多晶硅层被沉积到足以填充开口并形成基本平坦的表面的厚度。 沉积和图案化第二绝缘层以在节点接触件上形成具有垂直侧壁的部分。 沉积保形第二Si 3 N 4层并回蚀刻以在垂直侧壁上形成间隔物，并且将第一多晶硅层蚀刻到第一Si 3 N 4层。 使用HF酸选择性地除去第二绝缘层，而第一多晶硅和第一Si 3 N 4层防止蚀刻下面的第一SiO 2层。 沉积第二多晶硅层并将其回蚀以形成用于电容器底部电极的双气缸侧壁。 在热磷酸中除去第一和第二Si 3 N 4层。 电容器通过在底部电极上形成电极间电介质层而形成，并且为顶部电极沉积第三多晶硅层。
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2.发明授权Key-hole free process for high aspect ratio gap filling with reentrant spacer 有权无缝隙工艺，用于高长宽比间隙填充可重入间隔公开(公告)号：US07482278B1
公开(公告)日：2009-01-27
申请号：US09247974
申请日：1999-02-11
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31056 , H01L21/76837
摘要： A new method of depositing PE-oxide or PE-TEOS. An HDP-oxide is provided over a pattern of polysilicon. An etch back is performed to the deposited HDP-oxide, a layer of plasma-enhanced SiN is deposited. This PE-SiN is etched back leaving SiN spacers on the sidewalls of the poly pattern, further leaving a deposition of HDP-oxide on the top surface of the poly pattern. The profile of the holes within the poly pattern in such that the final layer of PE-oxide or PE-TEOS is deposited without resulting in the formation of keyholes in this latter layer.
摘要翻译： 一种沉积PE氧化物或PE-TEOS的新方法。 在多晶硅图案上提供HDP氧化物。 对沉积的HDP-氧化物进行回蚀刻，沉积一层等离子体增强的SiN。 该PE-SiN被回蚀刻，留下多边形图案的侧壁上的SiN间隔物，进一步在多晶型图案的顶表面上留下HDP氧化物。 多晶型图案中的孔的轮廓使得沉积最终的聚乙烯氧化物层或PE-TEOS层，而不会在后一层中形成键槽。
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3.发明授权Process to form a crown capacitor structure for a dynamic random access memory cell 有权形成用于动态随机存取存储器单元的冠电容器结构的过程
公开(公告)号：US06015733A
公开(公告)日：2000-01-18
申请号：US133356
申请日：1998-08-13
申请人： Yu-Hua Lee , James (Cheng-Ming) Wu
发明人： Yu-Hua Lee , James (Cheng-Ming) Wu
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , Y10S438/97
摘要： A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick insulator layer. Removal of the regions of polysilicon, residing on the top surface of the thick insulator layer, results in a crown shaped, polysilicon storage node structure, in the opening, in the thick insulator layer. The crown shaped, polysilicon storage node structure, was protected from the polysilicon removal procedure, by a photoresist plug, formed overlying the polysilicon layer, in the opening, in the thick insulator layer. The photoresist plug was formed via photoresist application, exposure, and the development of exposed photoresist regions.
摘要翻译： 已经开发了用于形成用于DRAM电容器结构的冠形多晶硅存储节点结构的工艺。 该工艺的特征在于，在厚的绝缘体层中，在厚的绝缘体层的顶表面以及开口的所有表面上沉积多晶硅层。 在厚的绝缘体层中，去除驻留在厚绝缘体层的顶表面上的多晶硅区域，导致在开口中的冠状多晶硅存储节点结构。 通过在厚的绝缘体层中的开口中形成在多晶硅层上的光致抗蚀剂塞，保护了冠状多晶硅存储节点结构的多晶硅去除程序。 通过光致抗蚀剂施加，曝光和曝光的光致抗蚀剂区域的显影来形成光致抗蚀剂插塞。
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公开(公告)号：US06323118B1
公开(公告)日：2001-11-27
申请号：US09114129
申请日：1998-07-13
IPC分类号： H01L214763
CPC分类号： H01L21/76816 , H01L21/31116 , H01L21/3185 , H01L21/76811 , H01L21/76813
摘要： A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer. A second dielectric layer and a second etch-stop layer are next formed sequentially over the first etch-stop layer. Contact/via hole pattern is etched into the first etch-stop layer using a first photoresist layer. A second photoresist layer, patterned with metal line trench pattern, is formed over the contact/via patterned first etch-stop layer. The contact/via hole openings are etched into the first dielectric layer until the second etch-stop layer is reached. Then, both the first and second etch-stop layers are etched through the openings. The openings in the first and second etch-stop layers are both extended by etching the second and first dielectric layers, respectively, until the former opening reaches the second etch-stop layer, and the latter reaches the underlying substructure of devices within the semiconductor substrate. Thus, a combination of contact via interconnects, without borders, and self-aligned with respect to metal lines with relaxed photolithographic tolerances is formed together and simultaneously using a modified dual damascene process having two etch-stop layers.
摘要翻译： 公开了一种用于使用具有两个蚀刻停止层的改进的双镶嵌工艺在一起形成自对准，无边界接触和通孔同时具有松弛光刻对准公差的方法。 在第一介电层上形成第一蚀刻停止层。 接下来在第一蚀刻停止层上依次形成第二介电层和第二蚀刻停止层。 使用第一光致抗蚀剂层将接触/通孔图案蚀刻到第一蚀刻停止层中。 在接触/经过图案化的第一蚀刻停止层上形成第二光致抗蚀剂层，其上形成有金属线沟槽图案。 接触/通孔开口被蚀刻到第一介电层中，直到达到第二蚀刻停止层。 然后，通过开口蚀刻第一和第二蚀刻停止层。 第一和第二蚀刻停止层中的开口都分别通过蚀刻第二和第一电介质层而延伸，直到前一个开口到达第二蚀刻停止层，并且后者到达半导体衬底内的器件的底层子结构 。 因此，一起形成了具有无边界的接触通孔互连和相对于具有松弛光刻公差的金属线自对准的组合，并且同时使用具有两个蚀刻停止层的改进的双镶嵌工艺。
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5.发明授权Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits 失效用于改善半导体集成电路粗糙形貌的化学/机械抛光均匀性的方法公开(公告)号：US06265315B1
公开(公告)日：2001-07-24
申请号：US09104030
申请日：1998-06-24
申请人： Yu-Hua Lee , James (Cheng-Ming) Wu
发明人： Yu-Hua Lee , James (Cheng-Ming) Wu
IPC分类号： H01L21302
CPC分类号： H01L21/76819 , H01L21/31055
摘要： A method for making a planar interlevel dielectric (ILD) layer, having improved thickness uniforming across the substrate surface, over a patterned electrically conducting layer is achieved. The method involves forming electrically conducting lines on which is deposited a conformal first insulating layer that is uniformly thick across the substrate. An etch-stop composed of Si3N4 is deposited and a second insulating layer, composed of SiO2 or a low-dielectric-constant insulator, is deposited. The second insulating layer is then partially chemically/mechanically polished back to within a few thousand Angstroms of the etch-stop layer. The remaining second insulating layer is then plasma etched back selectively to the etch-stop layer to form a planar surface having a uniformly thick first insulating layer over the electrically conducting lines. The contact openings or via holes can now etched to a uniform depth in the etch-stop layer and the first insulating layer across the substrate. This results in contact openings having a constant aspect ratio across the substrate, thereby resulting in more repeatable and reliable contact resistance (Rc).
摘要翻译： 实现了一种在图案化的导电层上制造平面层间电介质（ILD）层的方法，该层具有改善的跨衬底表面的均匀度。 该方法包括形成导电线，在其上沉积跨基板均匀厚的共形第一绝缘层。 沉积由Si 3 N 4构成的蚀刻停止层，并沉积由SiO 2或低介电常数绝缘体组成的第二绝缘层。 然后将第二绝缘层部分地化学/机械抛光回到蚀刻停止层的几千埃内。 然后将剩余的第二绝缘层等离子体蚀刻回蚀刻停止层，以形成在导电线上具有均匀厚的第一绝缘层的平坦表面。 接触开口或通孔现在可以在蚀刻停止层和穿过基底的第一绝缘层上蚀刻到均匀的深度。 这导致在基板上具有恒定纵横比的接触开口，从而导致更可重复和可靠的接触电阻（Rc）。
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6.发明授权Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure 有权自对准接触工艺为冠状动态随机存取存储器电容器结构公开(公告)号：US06274426B1
公开(公告)日：2001-08-14
申请号：US09257830
申请日：1999-02-25
IPC分类号： H01L218242
CPC分类号： H01L21/76831 , H01L21/31116 , H01L21/3212 , H01L21/76802 , H01L21/76897 , H01L27/10855 , H01L28/91
摘要： A process for fabricating a crown shaped, capacitor structure, in a SAC opening, featuring a silicon nitride spacer, located on the walls of a bottom portion of the SAC opening, has been developed. The process features forming a SAC opening in a thick silicon oxide layer, then repairing, or filling, seams or voids, that may be present in the thick silicon oxide layer, at the perimeter of the SAC opening, via formation of a silicon nitride spacer on the sides of the SAC opening. Subsequent processing features: the isotropic removal of a top portion of the silicon nitride spacer; the formation of a polysilicon storage node structure, in the SAC opening; and the recessing of a top portion of the thick silicon oxide layer, resulting in exposure of additional polysilicon storage node, surface area.
摘要翻译： 已经开发了一种用于制造位于SAC开口的底部的壁上的具有氮化硅间隔物的SAC开口中的冠状电容器结构的方法。 该工艺特征是在厚的氧化硅层中形成SAC开口，然后通过形成氮化硅间隔物在SAC开口的周边处形成可能存在于厚氧化硅层中的或者填充接缝或空隙 在SAC开幕的两边。 随后的处理特征：氮化硅间隔物的顶部的各向同性去除; 形成多晶硅存储节点结构，在SAC开放; 并且厚的氧化硅层的顶部凹陷，导致额外的多晶硅存储节点的曝光，表面积。
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