公开(公告)号：US06638813B1

公开(公告)日：2003-10-28

申请号：US10059825

申请日：2002-01-29

申请人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

发明人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11

摘要： A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.

摘要翻译： 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

公开(公告)号：US06376294B1

公开(公告)日：2002-04-23

申请号：US09755686

申请日：2001-01-08

申请人： Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Chen-Jong Wang

发明人： Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Chen-Jong Wang

IPC分类号： H01L218238

CPC分类号： H01L27/10891 ,  H01L21/823842 ,  H01L27/10894

摘要： A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region. At least one second mask layer portion is formed over the undoped poly segment within the LOGIC region and at least one third mask layer portion is formed over the doped poly segment in the portion of the stitch region within the DRAM region. The doped poly segment and undoped poly segment are etched to form: undoped poly periphery logic gate portions within the LOGIC region; doped poly dog-bone within the portion of the stitch region within the DRAM region; and doped poly word lines within the DRAM region. The second and third mask layer portions are stripped to expose the undoped poly periphery logic gate portions and the doped poly dog-bone.

摘要翻译： 一种用于在DRAM器件中制造狗骨的方法，包括以下步骤。 提供了具有形成有STI的上硅层的半导体结构。 半导体结构具有LOGIC区域和其间具有缝合区域的DRAM区域。 在半导体结构上形成多晶硅层。 掺杂剂选择性地注入到DRAM区域内的多晶硅区域中，并且DRAM区域内的线圈区域的部分，以形成掺杂的多段，以及逻辑区域内的未掺杂的多段，以及缝合区域的部分 在LOGIC区域内。 在掺杂的多段和未掺杂的多段上形成硬掩模，并且被图案化以仅在DRAM区域内的字线掺杂的多段上形成至少一个图案化的第一硬掩模部分。 至少一个第二掩模层部分形成在LOGIC区域内的未掺杂的多段上，并且至少一个第三掩模层部分形成在DRAM区域内的线迹区域的部分中的掺杂多晶片段上。 蚀刻掺杂的多段和未掺杂的多段以在逻辑区内形成未掺杂的多边形逻辑门部; 在DRAM区域内的线圈区域的部分内的掺杂多晶骨; 和在DRAM区域内的掺杂多晶字线。 剥离第二和第三掩模层部分以暴露未掺杂的多边形逻辑门部分和掺杂的多晶骨。

公开(公告)号：US20130020678A1

公开(公告)日：2013-01-24

申请号：US13188343

申请日：2011-07-21

申请人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L29/02 ,  H01L21/02

CPC分类号： H01L27/0207 ,  H01L28/40

摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.

摘要翻译： 公开了具有无取向去耦电容器的半导体器件及其制造方法。 在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。 至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

公开(公告)号：US08659121B2

公开(公告)日：2014-02-25

申请号：US13188343

申请日：2011-07-21

申请人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L23/62

CPC分类号： H01L27/0207 ,  H01L28/40

摘要： Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes at least one integrated circuit and at least one decoupling capacitor. The at least one decoupling capacitor is oriented in a different direction than the at least one integrated circuit is oriented.

摘要翻译： 公开了具有无取向去耦电容器的半导体器件及其制造方法。 在一个实施例中，半导体器件包括至少一个集成电路和至少一个去耦电容器。 至少一个去耦电容器被定向在与至少一个集成电路取向的方向不同的方向上。

公开(公告)号：US06420226B1

公开(公告)日：2002-07-16

申请号：US10020753

申请日：2001-12-12

申请人： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

发明人： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

IPC分类号： H01L218244

CPC分类号： H01L27/105 ,  H01L27/11 ,  H01L28/91 ,  H01L29/66181

摘要： A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

摘要翻译： 已经开发了用于单晶体管，RAM单元中的埋层叠层电容器结构的制造工艺。 该方法特征在于通过选择性干法蚀刻工艺形成形成在氧化硅填充的浅沟槽形状的顶部的自对准的环形存储节点开口。 选择性干蚀刻方法与随后的选择性湿法蚀刻程序结合，在环形存储节点开口和相邻的半导体顶表面的接合处产生半导体衬底的裸露部分，允许在该区域中产生重掺杂区域。 当在环形存储节点结构中形成存储节点结构时，以及在重掺杂区域上覆盖时，重掺杂区域的存在将节点与衬底电阻降低。

公开(公告)号：US06794254B1

公开(公告)日：2004-09-21

申请号：US10438646

申请日：2003-05-15

申请人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis J. Sinitsky

发明人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis J. Sinitsky

IPC分类号： H01L21336

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.

摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

公开(公告)号：US20050017285A1

公开(公告)日：2005-01-27

申请号：US10920492

申请日：2004-08-18

申请人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis Sinitsky

发明人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis Sinitsky

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.

摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

公开(公告)号：US06306767B1

公开(公告)日：2001-10-23

申请号：US09584111

申请日：2000-05-31

申请人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Ming-Hsiang Chiang

发明人： Kuo-Chyuan Tzeng ,  Tse-Liang Ying ,  Wen-Chuan Chiang ,  Ming-Hsiang Chiang

IPC分类号： H01L21302

CPC分类号： H01L27/10888 ,  H01L21/32139 ,  H01L27/10811

摘要： Within a method for forming a patterned layer there is first provided a topographic substrate. There is then formed conformally over the topographic substrate a blanket target layer formed of a target material, where the blanket target layer has a lower substantially horizontal portion, an upper substantially horizontal portion and an intermediate portion therebetween. There is then formed upon the lower substantially horizontal portion of the blanket target layer a first masking layer formed of a first masking material and formed upon the upper substantially horizontal portion of the blanket target layer a second masking layer formed of a second masking material. There is then etched, while employing an etch method having an enhanced sequential selectivity for the first masking material and the target material with respect to the second masking material, the first masking layer and the lower substantially horizontal portion of the blanket target layer to form a patterned target layer which leaves exposed a portion of the substrate beneath the lower horizontal portion of the blanket target layer while leaving unetched the upper substantially horizontal portion of the blanket target layer. The method is particularly useful for forming patterned capacitor plate layers.

摘要翻译： 在形成图案层的方法中，首先提供地形衬底。 然后，在地形基底上形成由目标材料形成的覆盖目标层，其中覆盖层目标层具有下部基本水平的部分，上部基本水平的部分和在其间的中间部分。 然后，在覆盖目标层的下部基本水平的部分上形成由第一掩模材料形成并形成在覆盖目标层的上部基本水平的部分上的第一掩蔽层，第二掩蔽层由第二掩蔽材料形成。 然后蚀刻，同时采用对于第一掩蔽材料和靶材料相对于第二掩蔽材料具有增强的顺序选择性的蚀刻方法，覆盖目标层的第一掩蔽层和下部基本水平的部分，以形成 图案化目标层，其在衬底目标层的下部水平部分的下方露出衬底的一部分，同时保留未覆盖的覆盖目标层的上部基本水平的部分。 该方法对于形成图案化电容器板层特别有用。

公开(公告)号：US07091543B2

公开(公告)日：2006-08-15

申请号：US10920492

申请日：2004-08-18

申请人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis J. Sinitsky

发明人： Kuo-Chyuan Tzeng ,  Ming-Hsiang Chiang ,  Wen-Chuan Chiang ,  Dennis J. Sinitsky

IPC分类号： H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10894

摘要： A new method to form DRAM cells in an integrated circuit device is achieved. The method comprises providing a substrate. A plurality of STI regions is formed in the substrate. The STI regions comprise trenches in the substrate. The trenches are filled with a first dielectric layer. All of the first dielectric layer is etched away from a first group of the STI regions to form open trenches while leaving the first dielectric layer in a second group of the STI regions. A second dielectric layer is formed overlying the substrate and lining the open trenches. A conductive layer is deposited overlying the second dielectric layer and completely filling the open trenches. The conductive layer is patterned to define DRAM transistor gates and to define DRAM capacitor top plates. Thereafter, ions are implanted into the substrate to form source and drain regions for the transistors.

摘要翻译： 实现了在集成电路器件中形成DRAM单元的新方法。 该方法包括提供基底。 在衬底中形成多个STI区。 STI区域包括衬底中的沟槽。 沟槽填充有第一介电层。 所有第一电介质层被蚀刻离开第一组STI区域以形成开放沟槽，同时将第一介电层留在STI区域的第二组中。 第二电介质层形成在衬底上并衬衬开放的沟槽。 沉积覆盖第二介电层并完全填充开放沟槽的导电层。 图案化导电层以限定DRAM晶体管栅极并且限定DRAM电容器顶板。 此后，将离子注入衬底以形成用于晶体管的源极和漏极区域。

公开(公告)号：US08617949B2

公开(公告)日：2013-12-31

申请号：US13267424

申请日：2011-10-06

申请人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

发明人： Kuo-Chi Tu ,  Wen-Chuan Chiang ,  Chen-Jong Wang

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system-on-chip device comprises a first capacitor in a first region, a second capacitor in a second region, and may further comprise a third capacitor in a third region, and any additional number of capacitors in additional regions. The capacitors may be of different shapes and sizes. A region may comprise more than one capacitor. Each capacitor in a region has a top electrode, a bottom electrode, and a capacitor insulator. The top electrodes of all the capacitors are formed in a common process, while the bottom electrodes of all the capacitors are formed in a common process. The capacitor insulator may have different number of sub-layers, formed with different materials or thickness. The capacitors may be formed in an inter-layer dielectric layer or in an inter-metal dielectric layer. The regions may be a mixed signal region, an analog region, and so forth.

摘要翻译： 片上系统装置包括第一区域中的第一电容器，第二区域中的第二电容器，并且还可以包括第三区域中的第三电容器，以及附加区域中的任何附加数量的电容器。 电容器可以具有不同的形状和尺寸。 区域可以包括多于一个的电容器。 区域中的每个电容器具有顶部电极，底部电极和电容器绝缘体。 所有电容器的顶部电极以公共工艺形成，而所有电容器的底部电极形成在共同的工艺中。 电容器绝缘体可以具有不同数量的亚层，形成不同的材料或厚度。 电容器可以形成在层间电介质层中或在金属间介电层中。 这些区域可以是混合信号区域，模拟区域等。