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    Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell
    1.
    发明授权
    Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell 有权
    形成复合间隔物以消除伪SRAM单元中的元件之间的多晶硅桁条的方法

    公开(公告)号：US06638813B1

    公开(公告)日：2003-10-28

    申请号：US10059825

    申请日：2002-01-29

    申请人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

    发明人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Kuo-Ching Huang

    IPC分类号： H01L218242

    CPC分类号： H01L28/60 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/76232 ,  H01L27/11

    摘要： A process for forming a composite insulator spacer on the sides of a buried stack capacitor structure, wherein the buried stack capacitor structure is located overlying a portion of an insulator filled, shallow trench isolation (STI) region, has been developed. A thin silicon nitride spacer is first formed on the sides of the completed buried stack capacitor structure, followed by deposition of a silicon oxide layer. An anisotropic dry etch procedure is next employed removing a top portion of the silicon oxide layer, and resulting in a partially defined silicon oxide spacer. A critical wet etch procedure is next used to remove the bottom portion of the silicon oxide layer, defining the final silicon oxide spacer of the composite insulator spacer, now comprised of a silicon oxide spacer on an underlying silicon nitride spacer. The wet etch procedure allows a gradual slope to be created at the composite insulator spacer—STI region interface, reducing the risk of leaving, or forming polysilicon residuals or stringers on the underlying surface, which can occur during definition of a MOSFET gate structure. The elimination of the polysilicon stringers reduces the risk of leakage between SRAM cell elements, such as buried stack capacitor structures, and MOSFET devices.

    摘要翻译： 已经开发了一种用于在掩埋叠层电容器结构的侧面上形成复合绝缘体间隔物的方法，其中埋层叠层电容器结构位于绝缘体填充的浅沟槽隔离（STI）区域的一部分上方。 首先在完成的掩埋堆叠电容器结构的侧面上形成薄的氮化硅间隔物，然后沉积氧化硅层。 接下来，使用各向异性干蚀刻工艺去除氧化硅层的顶部，并产生部分限定的氧化硅间隔物。 接下来使用关键的湿法蚀刻工艺来去除氧化硅层的底部，限定复合绝缘垫片的最终氧化硅隔离物，现在由下面的氮化硅间隔物上的氧化硅间隔物构成。 湿蚀刻工艺允许在复合绝缘体间隔件-ST区域界面处产生逐渐的斜率，从而降低在MOSFET栅极结构的定义期间可能发生的在下表面上的离开风险或形成多晶硅残余物或桁条。 多晶硅桁架的消除降低了诸如掩埋堆叠电容器结构的SRAM单元元件和MOSFET器件之间的泄漏的风险。

    Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process
    2.
    发明授权
    Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process 有权
    在嵌入式DRAM工艺中，针脚区域的字线绑扎接触定义多边形骨的方法

    公开(公告)号：US06376294B1

    公开(公告)日：2002-04-23

    申请号：US09755686

    申请日：2001-01-08

    申请人： Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Chen-Jong Wang

    发明人： Kuo-Chyuan Tzeng ,  Wen-Chuan Chiang ,  Wen-Cheng Chen ,  Chen-Jong Wang

    IPC分类号： H01L218238

    CPC分类号： H01L27/10891 ,  H01L21/823842 ,  H01L27/10894

    摘要： A method for fabricating a dog-bone in a DRAM device, comprising the following steps. A semiconductor structure having an upper silicon layer with STIs formed therein is provided. The semiconductor structure has a LOGIC region and a DRAM region with a stitch region therebetween. A polysilicon layer is formed over the semiconductor structure. A dopant is selectively implanted in the polysilicon region within the DRAM region, and the portion of the stitch region within the DRAM region, to form a doped poly segment, and an undoped poly segment within the LOGIC region, and the portion of the stitch region within the LOGIC region. A hard mask is formed over the doped poly segment and the undoped poly segment and patterned to form at least one patterned first hard mask portion only over the word line doped poly segment within the DRAM region. At least one second mask layer portion is formed over the undoped poly segment within the LOGIC region and at least one third mask layer portion is formed over the doped poly segment in the portion of the stitch region within the DRAM region. The doped poly segment and undoped poly segment are etched to form: undoped poly periphery logic gate portions within the LOGIC region; doped poly dog-bone within the portion of the stitch region within the DRAM region; and doped poly word lines within the DRAM region. The second and third mask layer portions are stripped to expose the undoped poly periphery logic gate portions and the doped poly dog-bone.

    摘要翻译： 一种用于在DRAM器件中制造狗骨的方法，包括以下步骤。 提供了具有形成有STI的上硅层的半导体结构。 半导体结构具有LOGIC区域和其间具有缝合区域的DRAM区域。 在半导体结构上形成多晶硅层。 掺杂剂选择性地注入到DRAM区域内的多晶硅区域中，并且DRAM区域内的线圈区域的部分，以形成掺杂的多段，以及逻辑区域内的未掺杂的多段，以及缝合区域的部分 在LOGIC区域内。 在掺杂的多段和未掺杂的多段上形成硬掩模，并且被图案化以仅在DRAM区域内的字线掺杂的多段上形成至少一个图案化的第一硬掩模部分。 至少一个第二掩模层部分形成在LOGIC区域内的未掺杂的多段上，并且至少一个第三掩模层部分形成在DRAM区域内的线迹区域的部分中的掺杂多晶片段上。 蚀刻掺杂的多段和未掺杂的多段以在逻辑区内形成未掺杂的多边形逻辑门部; 在DRAM区域内的线圈区域的部分内的掺杂多晶骨; 和在DRAM区域内的掺杂多晶字线。 剥离第二和第三掩模层部分以暴露未掺杂的多边形逻辑门部分和掺杂的多晶骨。

    Method of defining a buried stack capacitor structure for a one transistor RAM cell
    3.
    发明授权
    Method of defining a buried stack capacitor structure for a one transistor RAM cell 有权
    定义一个晶体管RAM单元的掩埋堆叠电容器结构的方法

    公开(公告)号：US06420226B1

    公开(公告)日：2002-07-16

    申请号：US10020753

    申请日：2001-12-12

    申请人： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

    发明人： Wen-Cheng Chen ,  Kuo-Ching Huang ,  Chen-Jong Wang ,  Wen-Chuan Chiang

    IPC分类号： H01L218244

    CPC分类号： H01L27/105 ,  H01L27/11 ,  H01L28/91 ,  H01L29/66181

    摘要： A process for fabricating a buried stack capacitor structure, to be used in a one transistor, RAM cell, has been developed. The process features formation of a self-aligned, ring shaped storage node opening, formed in a top portion of an silicon oxide filled, shallow trench shape, via a selective dry etch procedure. The selective dry etch procedure in combination with subsequent selective wet etch procedures, create bare portions of semiconductor substrate at the junction of the ring shaped storage node opening and the adjacent top surface of semiconductor, allowing a heavily doped region to be created in this region. The presence of the heavily doped region reduces the node to substrate resistance encountered when a storage node structure is formed in the ring shaped storage node structure, as well as on the overlying the heavily doped region.

    摘要翻译： 已经开发了用于单晶体管，RAM单元中的埋层叠层电容器结构的制造工艺。 该方法特征在于通过选择性干法蚀刻工艺形成形成在氧化硅填充的浅沟槽形状的顶部的自对准的环形存储节点开口。 选择性干蚀刻方法与随后的选择性湿法蚀刻程序结合，在环形存储节点开口和相邻的半导体顶表面的接合处产生半导体衬底的裸露部分，允许在该区域中产生重掺杂区域。 当在环形存储节点结构中形成存储节点结构时，以及在重掺杂区域上覆盖时，重掺杂区域的存在将节点与衬底电阻降低。

    One-transistor RAM approach for high density memory application
    4.
    发明授权
    One-transistor RAM approach for high density memory application 有权
    用于高密度存储器应用的单晶体管RAM方法

    公开(公告)号：US06661043B1

    公开(公告)日：2003-12-09

    申请号：US10400401

    申请日：2003-03-27

    申请人： Kuo-Ching Huang ,  Wen-Cheng Chen ,  Wen-Chuan Chiang ,  Kuo-Chuang Tseng

    发明人： Kuo-Ching Huang ,  Wen-Cheng Chen ,  Wen-Chuan Chiang ,  Kuo-Chuang Tseng

    IPC分类号： H01L218242

    CPC分类号： H01L27/1085 ,  H01L27/1087

    摘要： A new method is provided for the creation of a 1T RAM cell. Standard processing is applied to create STI trenches in the surface of a substrate, N2 implantations are performed into the sidewalls of the STI trenches. A layer of lining oxide is created, the implanted N2 interacts with the lining oxide to form SiON over exposed surfaces of the STI trenches. STI oxide is deposited and polished, filling the STI trenches there-with. Crown patterning is performed to define capacitor areas, the crown patterning stops on a layer of etch stop material and the created SION and partially removes STI oxide from the STI trenches. Layers of etch stop material, exposed SiON and pad oxide are removed, exposing the surface of the silicon substrate, the etched layers of STI oxide are not affected by this removal. A layer of SAC oxide is grown, n-well and p-well implantations are performed into the surface of the substrate. The layer of SAC oxide is removed, gate oxide is grown, polysilicon is deposited and patterned and etched, forming polysilicon gate material and polysilicon top plate of the capacitor. Standard processing is further applied to complete the 1T-RAM cell by providing gate spacers and impurity implantations for the gate electrode, by saliciding contact surfaces and by providing contacts to the points of contact of the cell.

    摘要翻译： 提供了一种用于创建1T RAM单元的新方法。 施加标准处理以在衬底的表面中产生STI沟槽，在STI沟槽的侧壁中进行N2注入。 产生衬里氧化层，注入的N 2与衬里氧化物相互作用以在STI沟槽的暴露表面上形成SiON。 沉积和抛光STI氧化物，在那里填充STI沟槽。 进行冠图案化以限定电容器区域，冠图案停止在蚀刻停止材料层上，并且所产生的SION并且部分地从STI沟槽去除STI氧化物。 蚀刻停止材料层，暴露的SiON和衬垫氧化物层被去除，暴露硅衬底的表面，STI氧化物的蚀刻层不受该去除的影响。 生长一层SAC氧化物，n阱和p阱注入进行到衬底的表面。 去除SAC氧化物层，生长栅极氧化物，沉积多晶硅并进行图案化和蚀刻，形成电容器的多晶硅栅极材料和多晶硅顶板。 进一步应用标准处理，通过为栅电极提供栅极间隔物和杂质注入，通过对接触表面进行喷淋并且通过提供与电池的接触点的接触来完成1T-RAM单元。

    Electronic device
    6.
    发明授权
    Electronic device 有权
    电子设备

    公开(公告)号：US08482914B2

    公开(公告)日：2013-07-09

    申请号：US13304693

    申请日：2011-11-28

    申请人： Wen-Cheng Chen

    发明人： Wen-Cheng Chen

    IPC分类号： G06F1/16

    CPC分类号： G06F1/187 ,  G11B33/124

    摘要： An electronic device with multi-phase mechanism including a host, a storage device and a carriage is provided in the present invention. The storage device is slidably disposed in the host and adapted to be pulled out from the host. The carriage is slidably disposed in the storage device and adapted to be pulled out from the storage device. Through the storage device slidably disposing in the host and being adapted to be pulled out from the host, it facilitates the user to take or replace a content from the storage device. When the carriage is moved out from the storage device in a first phase and then the storage device is pulled out from the host in a second phase, the content in the storage device is taken out.

    摘要翻译： 本发明提供一种具有主机，存储装置和滑架的多相机构的电子装置。 存储装置可滑动地设置在主机中并且适于从主机被拉出。 滑架可滑动地设置在存储装置中并且适于从存储装置拉出。 通过可滑动地布置在主机中并适于从主机拔出的存储装置，便于用户从存储装置中取出或更换内容。 当第一阶段将托架从存储装置移出，然后在第二阶段将存储装置从主机中拉出时，取出存储装置中的内容。

    REVERSE CONNECTION MTJ CELL FOR STT MRAM
    7.
    发明申请
    REVERSE CONNECTION MTJ CELL FOR STT MRAM 有权
    反向连接用于STT MRAM的MTJ单元

    公开(公告)号：US20110122674A1

    公开(公告)日：2011-05-26

    申请号：US12626092

    申请日：2009-11-25

    申请人： CHUN-JUNG LIN ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    发明人： CHUN-JUNG LIN ,  Yu-Jen Wang ,  Ya-Chen Kao ,  Wen-Cheng Chen ,  Ming-Te Liu

    IPC分类号： G11C11/22 ,  H01L29/82 ,  H01L21/28

    CPC分类号： H01L43/08 ,  G11C11/16 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/12

    摘要： Apparatus and methods are disclosed herein for a reverse-connection STT MTJ element of a MRAM to overcome the source degeneration effect when switching the magnetization of the MTJ element from the parallel to the anti-parallel direction. A memory cell of a MRAM having a reverse-connection MTJ element includes a switching device having a source, a gate, and a drain, and a reverse-connection MTJ device having a free layer, a fixed layer, and an insulator layer interposed between the free layer and the fixed layer. The free layer of the reverse-connection MTJ device is connected to the drain of the switching device and the fixed layer is connected to a bit line (BL). The reverse-connection MTJ device applies the lower IMTJ capability of the memory cell caused by the source degeneration effect to the less stringent IMTJ(AP->P) while preserving the higher IMTJ capability for the more demanding IMTJ(P->AP).

    摘要翻译： 本文公开了用于MRAM的反向连接STT MTJ元件的装置和方法，以在将MTJ元件的磁化从平行方向切换到反平行方向时克服源退化效应。 具有反向连接MTJ元件的MRAM的存储单元包括具有源极，栅极和漏极的开关器件和具有自由层，固定层和绝缘体层的反向连接MTJ器件， 自由层和固定层。 反连接MTJ器件的自由层连接到开关器件的漏极，固定层连接到位线（BL）。 反向连接MTJ设备将由源退化效应引起的存储器单元的较低IMTJ能力应用于较不严格的IMTJ（AP-> P），同时为更苛刻的IMTJ（P-> AP）保持较高的IMTJ能力。