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    Method and apparatus for communication between two or more processing elements
    1.
    发明申请
    Method and apparatus for communication between two or more processing elements 失效
    用于在两个或多个处理元件之间进行通信的方法和装置

    公开(公告)号：US20060225074A1

    公开(公告)日：2006-10-05

    申请号：US11095341

    申请日：2005-03-30

    申请人： Kushagra Vaid ,  John Crawford ,  Allen Baum

    发明人： Kushagra Vaid ,  John Crawford ,  Allen Baum

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/522

    摘要： A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.

    摘要翻译： 一种用于在多个程序线程之间执行屏障同步的技术。 更具体地，本发明的至少一个实施例使用可以被更新和重新分配的屏障寄存器内的位来跟踪与多个程序线程相关联的完成的任务，而不会像现有技术那样产生总线流量。

    Method and apparatus for communication between two or more processing elements
    2.
    发明授权
    Method and apparatus for communication between two or more processing elements 失效
    用于在两个或多个处理元件之间进行通信的方法和装置

    公开(公告)号：US08645959B2

    公开(公告)日：2014-02-04

    申请号：US11095341

    申请日：2005-03-30

    申请人： Kushagra Vaid ,  John Crawford ,  Allen Baum

    发明人： Kushagra Vaid ,  John Crawford ,  Allen Baum

    IPC分类号： G06F9/46

    CPC分类号： G06F9/52 ,  G06F9/522

    摘要： A technique for performing barrier synchronization among a plurality of program threads. More particularly, at least one embodiment of the invention keeps track of completed tasks associated with a number of program threads using bits within a barrier register that can be updated and reassigned without incurring the amount of bus traffic as in the prior art.

    摘要翻译： 一种用于在多个程序线程之间执行屏障同步的技术。 更具体地，本发明的至少一个实施例使用可以被更新和重新分配的屏障寄存器内的位来跟踪与多个程序线程相关联的完成的任务，而不会像现有技术那样产生总线流量。

    Transaction based shared data operations in a multiprocessor environment
    3.
    发明申请
    Transaction based shared data operations in a multiprocessor environment 有权
    多处理器环境中基于事务的共享数据操作

    公开(公告)号：US20060161740A1

    公开(公告)日：2006-07-20

    申请号：US11027623

    申请日：2004-12-29

    申请人： Sailesh Kottapalli ,  John Crawford ,  Kushagra Vaid

    发明人： Sailesh Kottapalli ,  John Crawford ,  Kushagra Vaid

    IPC分类号： G06F13/00

    CPC分类号： G06F9/528 ,  G06F9/3834 ,  G06F9/544

    摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

    摘要翻译： 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

    POWER-CAPPING BASED ON UPS CAPACITY
    4.
    发明申请
    POWER-CAPPING BASED ON UPS CAPACITY 有权
    基于UPS容量的电源接收

    公开(公告)号：US20120331317A1

    公开(公告)日：2012-12-27

    申请号：US13168983

    申请日：2011-06-26

    申请人： Harry R. Rogers ,  Kushagra Vaid ,  Mark E. Shaw ,  Badriddine Khessib ,  Bryan Kelly ,  Matthew Faist

    发明人： Harry R. Rogers ,  Kushagra Vaid ,  Mark E. Shaw ,  Badriddine Khessib ,  Bryan Kelly ,  Matthew Faist

    IPC分类号： G06F1/32

    CPC分类号： G06F1/30 ,  G06F1/28 ,  G06F1/3212 ,  H02J3/14 ,  Y02D10/174

    摘要： The power draw of equipment in a data center may be capped in order to keep the power draw under the capacity of the Uninterruptable Power Supply (UPS) that serves the data center. The current capacity of the UPS may be estimated, and the equipment may be controlled so as to keep the equipment's power draw under that current capacity. Factors that may affect the estimate of the UPS's current capacity include the history of temperature and humidity to which the UPS has been subject, and charge/discharge history of the UPS. Factors that may affect the decision of which equipment to throttle to a lower power level include: the current power load at the data center, the type of software that each server is running, and the demand for that software.

    摘要翻译： 数据中心设备的功耗可能会被限制，以便在为数据中心服务的不间断电源（UPS）的容量内保持功耗。 可以估计UPS的当前容量，并且可以控制设备以便将设备的功率降低到当前容量之下。 可能影响UPS当前容量估算的因素包括UPS遭受的温度和湿度历史以及UPS的充放电历史。 可能影响哪些设备降低功率水平的决定因素包括：数据中心当前的电力负载，每个服务器运行的软件类型以及该软件的需求。

    Application-transparent hybridized caching for high-performance storage
    5.
    发明授权
    Application-transparent hybridized caching for high-performance storage 有权
    应用透明的混合缓存，用于高性能存储

    公开(公告)号：US08321630B1

    公开(公告)日：2012-11-27

    申请号：US12695552

    申请日：2010-01-28

    申请人： Kushagra Vaid ,  Sompong Paul Olarig

    发明人： Kushagra Vaid ,  Sompong Paul Olarig

    IPC分类号： G06F12/00

    CPC分类号： G06F3/061 ,  G06F3/0655 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0893 ,  G06F2212/1016 ,  G06F2212/2146 ,  G06F2212/217 ,  G06F2212/225 ,  G06F2212/312 ,  G11C7/1072 ,  G11C11/40615 ,  G11C16/102

    摘要： Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.

    摘要翻译： 提供了系统，装置和计算机实现的方法，用于使用磁性和固态存储介质的高速缓冲存储器的杂交。 固态高速缓存控制器设备可以耦合到主机计算系统，以对使用该系统的高级应用是透明的方式来最大化系统的效率。 该装置包括关联存储器组件和固态高速缓存控制组件。 固态存储器被配置为存储主机读取操作的数据块。 如果请求主机读取操作，则控制器与固态缓存存储器控制器进行通信，以确定标签阵列数据结构是否指示所请求数据块的缓存副本在固态存储器中可用。

    Transaction based shared data operations in a multiprocessor environment
    6.
    发明授权
    Transaction based shared data operations in a multiprocessor environment 有权
    多处理器环境中基于事务的共享数据操作

    公开(公告)号：US07984248B2

    公开(公告)日：2011-07-19

    申请号：US11027623

    申请日：2004-12-29

    申请人： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

    发明人： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

    IPC分类号： G06F12/00

    CPC分类号： G06F9/528 ,  G06F9/3834 ,  G06F9/544

    摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

    摘要翻译： 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。