公开(公告)号：US07485490B2

公开(公告)日：2009-02-03

申请号：US11286970

申请日：2005-11-22

Applicant: Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

Inventor： Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: Disclosed is a stacking structure of semiconductor chips and semiconductor package using it, capable of achieving an electric insulation even if a conductive wire makes contact with a lower surface of an upper semiconductor chip, while reducing a total thickness thereof and preventing damage. The stacking structure has a substrate formed with a plurality of circuit patterns; a first semiconductor chip bonded to an upper surface of the substrate and having a first plane and a second plane formed with a plurality of input/output pads; a spacer bonded to the second plane of the first semiconductor chip; a second semiconductor chip having first and second planes, the second plane being formed with a plurality of input/output pads, the first plane being provided with an insulating member so as to allow the second semiconductor chip to be bonded to the spacer, a first conductive wire for connecting the input/output pads of the first semiconductor chip to the circuit patterns of the substrate; and a second conductive wire for connecting the input/output pads of the second semiconductor chip to the circuit patterns of the substrate.

Abstract translation: 公开了半导体芯片的堆叠结构和使用它的半导体封装，即使导线与上半导体芯片的下表面接触而能够实现电绝缘，同时减小其总厚度并防止损坏。 堆叠结构具有形成有多个电路图案的基板; 第一半导体芯片，其结合到所述基板的上表面并具有形成有多个输入/输出焊盘的第一平面和第二平面; 连接到第一半导体芯片的第二平面的间隔物; 具有第一和第二平面的第二半导体芯片，所述第二平面形成有多个输入/输出焊盘，所述第一平面设置有绝缘构件，以允许所述第二半导体芯片与所述间隔件接合， 导线，用于将第一半导体芯片的输入/输出焊盘连接到衬底的电路图案; 以及用于将第二半导体芯片的输入/输出焊盘连接到衬底的电路图案的第二导线。

公开(公告)号：US20110089564A1

公开(公告)日：2011-04-21

申请号：US12927533

申请日：2010-11-16

Applicant: Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

Inventor： Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

IPC: H01L23/498

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Abstract translation: 半导体封装及其制造方法具有基板。 第一半导体芯片耦合到衬底的表面。 第一半导体芯片本质上具有基本平坦的第一和第二表面。 粘合剂层耦合到第一半导体芯片的第二表面。 进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。 绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。 第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

公开(公告)号：US20090134507A1

公开(公告)日：2009-05-28

申请号：US12317649

申请日：2008-12-23

Applicant: Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

Inventor： Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

IPC: H01L23/52

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Abstract translation: 半导体封装及其制造方法具有基板。 第一半导体芯片耦合到衬底的表面。 第一半导体芯片本质上具有基本平坦的第一和第二表面。 粘合剂层耦合到第一半导体芯片的第二表面。 进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。 绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。 第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

公开(公告)号：US08528290B2

公开(公告)日：2013-09-10

申请号：US13258734

申请日：2010-03-12

Applicant: Kwang Seok Oh

Inventor： Kwang Seok Oh

IPC: E04B2/00

CPC classification number: E04F15/04 ,  E04F15/02038 ,  E04F15/102 ,  E04F2201/0153 ,  E04F2201/0161 ,  E04F2201/03

Abstract: Disclosed is a floorboard to provide simplified assembly of flooring panels without damage and achieve enhanced horizontal coupling force. The floorboard includes a tongue part provided at a first flooring panel and a recessed part provided at a second flooring panel. The tongue part includes a tongue protrusion, a tongue bottom portion, and a raised retaining portion protruding downward from the tongue bottom portion. The recessed part includes an upper lip caught by the tongue protrusion when the tongue part is inserted into the recessed part, a lower lip, a raised portion protruding upward from an end of the lower lip, and a guide wall defining an inner wall of the recessed part and having the same contour as an arc drawn by an end of the tongue protrusion as the tongue part introduced between the upper and lower lips is pivotally rotated.

Abstract translation: 公开了一种地板，用于简化地板镶板的组装而不损坏并实现增强的水平联接力。 地板包括设置在第一地板面板上的舌部和设置在第二地板面板上的凹部。 舌部包括舌突起，舌底部和从舌底部向下突出的凸起保持部。 凹部包括当舌部被插入到凹部中时由舌突起捕获的上唇，下唇，从下唇的端部向上突出的凸起部以及限定了下唇的内壁的引导壁 并且具有与由舌状部分引入上下唇之间的舌部突出部的一端的弧形相同的轮廓。

公开(公告)号：US20120317916A1

公开(公告)日：2012-12-20

申请号：US13582448

申请日：2011-02-14

Applicant: Kwang Seok Oh

Inventor： Kwang Seok Oh

IPC: E04B5/00

CPC classification number: E04F15/02 ,  E04F2201/0138 ,  E04F2201/0153 ,  E04F2201/0169 ,  E04F2201/0552

Abstract: Provided are a flooring material and a rotational body used therewith which are adapted to improve quality reliability in flooring materials by stably providing not only a fastening force in the horizontal direction but also a fastening force in the vertical direction when flooring panels are assembled with each other, thereby facilitating assembly of the flooring panels and strengthening the joining force due to assembly. To this end, the flooring material according to one embodiment of the present invention is a flooring material formed by assembling a plurality of flooring panels together, comprising: a recessed part which is formed at one end of a flooring panel; a tongue part which is formed so as to assemble in the recessed part at one end of another flooring panel; an accommodating recess which is formed in the recessed part; and a rotational body which is accommodated so as to be able to rotate in the accommodating recess and secures the tongue part by being rotated in one direction when the tongue part is assembled in the recessed part, and releases the tongue part from the secured state by being rotated in the opposite direction when the tongue part is separated from the recessed part.

Abstract translation: 本发明提供一种地板材料和旋转体，其适于通过在地板镶板彼此组装时不仅稳定地提供水平方向上的紧固力而且还提供垂直方向上的紧固力，从而提高地板材料的质量可靠性 从而便于地板镶板的组装和加强由于组装而产生的接合力。 为此，根据本发明的一个实施方案的地板材料是通过将多个地板镶嵌在一起而形成的地板材料，包括：形成在地板镶板的一端的凹部; 舌部，其形成为在另一地板镶板的一端的凹部中组装; 形成在所述凹部的容纳凹部; 以及旋转体，其容纳成能够在所述容纳凹部中旋转并且当所述舌部组装在所述凹部中时沿着一个方向旋转来固定所述舌部，并且通过所述舌部从所述固定状态释放所述舌部 当舌部与凹部分离时，沿相反方向旋转。

公开(公告)号：US08143727B2

公开(公告)日：2012-03-27

申请号：US12927533

申请日：2010-11-16

Applicant: Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

Inventor： Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/28 ,  H01L23/02

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Abstract translation: 半导体封装及其制造方法具有基板。 第一半导体芯片耦合到衬底的表面。 第一半导体芯片本质上具有基本平坦的第一和第二表面。 粘合剂层耦合到第一半导体芯片的第二表面。 进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。 绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。 第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

公开(公告)号：US08590250B2

公开(公告)日：2013-11-26

申请号：US13582448

申请日：2011-02-14

Applicant: Kwang Seok Oh

Inventor： Kwang Seok Oh

IPC: E04F15/02

CPC classification number: E04F15/02 ,  E04F2201/0138 ,  E04F2201/0153 ,  E04F2201/0169 ,  E04F2201/0552

Abstract: Provided are a flooring material and a rotational body used therewith which are adapted to improve quality reliability in flooring materials by stably providing not only a fastening force in the horizontal direction but also a fastening force in the vertical direction when flooring panels are assembled with each other, thereby facilitating assembly of the flooring panels and strengthening the joining force due to assembly.

Abstract translation: 本发明提供一种地板材料和旋转体，其适于通过在地板镶板彼此组装时不仅稳定地提供水平方向上的紧固力而且还提供垂直方向的紧固力，从而提高地板材料的质量可靠性 从而便于地板镶板的组装和加强由于组装而产生的接合力。

公开(公告)号：US20120017534A1

公开(公告)日：2012-01-26

申请号：US13258734

申请日：2010-03-12

Applicant: Kwang Seok Oh

Inventor： Kwang Seok Oh

IPC: E04B5/00

CPC classification number: E04F15/04 ,  E04F15/02038 ,  E04F15/102 ,  E04F2201/0153 ,  E04F2201/0161 ,  E04F2201/03

Abstract: Disclosed is a floorboard to provide simplified assembly of flooring panels without damage and achieve enhanced horizontal coupling force. The floorboard includes a tongue part provided at a first flooring panel and a recessed part provided at a second flooring panel. The tongue part includes a tongue protrusion, a tongue bottom portion, and a raised retaining portion protruding downward from the tongue bottom portion. The recessed part includes an upper lip caught by the tongue protrusion when the tongue part is inserted into the recessed part, a lower lip, a raised portion protruding upward from an end of the lower lip, and a guide wall defining an inner wall of the recessed part and having the same contour as an arc drawn by an end of the tongue protrusion as the tongue part introduced between the upper and lower lips is pivotally rotated.

Abstract translation: 公开了一种地板，用于简化地板镶板的组装而不损坏并实现增强的水平联接力。 地板包括设置在第一地板面板上的舌部和设置在第二地板面板上的凹部。 舌部包括舌突起，舌底部和从舌底部向下突出的凸起保持部。 凹部包括当舌部被插入到凹部中时由舌突起捕获的上唇，下唇，从下唇的端部向上突出的凸起部以及限定了下唇的内壁的引导壁 并且具有与由舌状部分引入上下唇之间的舌部突出部的一端的弧形相同的轮廓。

公开(公告)号：US07863723B2

公开(公告)日：2011-01-04

申请号：US12317649

申请日：2008-12-23

Applicant: Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

Inventor： Kwang Seok Oh ,  Jong Wook Park ,  Young Kuk Park ,  Byoung Youl Min

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor package and a method of producing the same has a substrate. A first semiconductor chip is coupled to a surface of the substrate. The first semiconductor chip has a first and second surfaces which are substantially flat in nature. An adhesive layer is coupled to the second surface of the first semiconductor chip. A second semiconductor chip having first and second surfaces which are substantially flat in nature is further provided. An insulator is coupled to the first surface of the second semiconductor chip for preventing shorting of wirebonds. The second semiconductor chip is coupled to the adhesive layer by the insulator coupled to the first surface thereof.

Abstract translation: 半导体封装及其制造方法具有基板。 第一半导体芯片耦合到衬底的表面。 第一半导体芯片本质上具有基本平坦的第一和第二表面。 粘合剂层耦合到第一半导体芯片的第二表面。 进一步提供第二半导体芯片，其具有基本上平坦的第一表面和第二表面。 绝缘体耦合到第二半导体芯片的第一表面，以防止引线短路。 第二半导体芯片通过耦合到其第一表面的绝缘体耦合到粘合剂层。

公开(公告)号：US20090117705A1

公开(公告)日：2009-05-07

申请号：US12163844

申请日：2008-06-27

Applicant: Kwang Seok Oh

Inventor： Kwang Seok Oh

IPC: H01L21/762

CPC classification number: H01L21/76232

Abstract: The present invention relates to a method of forming isolation layers of a semiconductor device. According to a method of forming isolation layers of a semiconductor device in accordance with an aspect of the present invention, a tunnel insulating layer, a charge trap layer, and a hard mask layer are sequentially formed over a semiconductor substrate. First trenches are formed by etching the hard mask layer, the charge trap layer, the tunnel insulating layer, and the semiconductor substrate. A spacer layer is formed on the entire surface including the first trenches. Second trenches are formed by etching the spacer layer, which is formed at a bottom of the first trenches, and the semiconductor substrate. An insulating layer for isolation is formed on the entire surface including the second trenches.

Abstract translation: 本发明涉及形成半导体器件隔离层的方法。 根据本发明的一个方面的形成半导体器件的隔离层的方法，在半导体衬底上依次形成隧道绝缘层，电荷阱层和硬掩模层。 通过蚀刻硬掩模层，电荷阱层，隧道绝缘层和半导体衬底形成第一沟槽。 在包括第一沟槽的整个表面上形成间隔层。 通过蚀刻形成在第一沟槽的底部的间隔层和半导体衬底来形成第二沟槽。 在包括第二沟槽的整个表面上形成用于隔离的绝缘层。