公开(公告)号：US08247788B2

公开(公告)日：2012-08-21

申请号：US12659175

申请日：2010-02-26

申请人： Kwang-soo Seol ,  Yoon-dong Park ,  Deok-kee Kim ,  Sang-jun Choi

发明人： Kwang-soo Seol ,  Yoon-dong Park ,  Deok-kee Kim ,  Sang-jun Choi

IPC分类号： H01L45/00

CPC分类号： H01L27/2445 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.

摘要翻译： 非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层 电极线。 所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体 导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

公开(公告)号：US20100237312A1

公开(公告)日：2010-09-23

申请号：US12659175

申请日：2010-02-26

申请人： Kwang-soo Seol ,  Yoon-dong Park ,  Deok-kee Kim ,  Sang-jun Choi

发明人： Kwang-soo Seol ,  Yoon-dong Park ,  Deok-kee Kim ,  Sang-jun Choi

IPC分类号： H01L45/00

CPC分类号： H01L27/2445 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The nonvolatile memory device includes at least one pair of first electrode lines, at least one device structure disposed between the at least one pair of first electrode lines and a dielectric layer disposed between the at least one device structure and the at least one pair of first electrode lines. The at least one device structure includes a second electrode line including a first conductive type semiconductor, a resistance changing material layer adjacent to the second electrode line, a channel adjacent to the resistance changing material layer and including a second conductive type semiconductor different from the first conductive type semiconductor and a third electrode line adjacent to the channel and including the first conductive type semiconductor.

摘要翻译： 非易失性存储器件包括至少一对第一电极线，设置在至少一对第一电极线之间的至少一个器件结构和设置在该至少一个器件结构与至少一对第一电极线之间的电介质层 电极线。 所述至少一个器件结构包括第二电极线，所述第二电极线包括第一导电类型半导体，与所述第二电极线相邻的电阻改变材料层，与所述电阻变化材料层相邻的通道，并且包括不同于所述第一导电类型的第一导电型半导体 导电型半导体和与沟道相邻的第三电极线，并且包括第一导电型半导体。

公开(公告)号：US20100012186A1

公开(公告)日：2010-01-21

申请号：US12436832

申请日：2009-05-07

申请人： Yoon-dong Park ,  Kwang-soo Seol ,  Deok-kee Kim ,  Won-joo Kim ,  Young-gu Jin ,  Seung-hoon Lee ,  Suk-pil Kim

发明人： Yoon-dong Park ,  Kwang-soo Seol ,  Deok-kee Kim ,  Won-joo Kim ,  Young-gu Jin ,  Seung-hoon Lee ,  Suk-pil Kim

IPC分类号： H01L31/00

CPC分类号： H01L35/32 ,  H01L31/0547 ,  H02S10/10 ,  Y02E10/52

摘要： Provided is a bulb-type light concentrated solar cell module that includes a reflective mirror unit that is concavely formed to convergingly reflect sunlight and has a first hole on a bottom thereof; a solar cell that generates electrical energy in response to light received from the reflective mirror unit; a socket that blocks the first hole at a lower part of the reflective mirror unit and is fixed on the reflective mirror unit; and a power control unit that is electrically connected to the solar cell to generate electricity in the socket.

摘要翻译： 本发明提供一种灯泡型光集中太阳能电池模块，其包括反射镜单元，该反射镜单元凹入地形成以会聚地反射太阳光，并且在其底部具有第一孔; 太阳能电池，其响应于从所述反射镜单元接收的光产生电能; 插座，其阻挡反射镜单元的下部的第一孔并固定在反射镜单元上; 以及电连接到太阳能电池以在插座中发电的电力控制单元。

公开(公告)号：US07675786B2

公开(公告)日：2010-03-09

申请号：US11898709

申请日：2007-09-14

申请人： Sang-jin Park ,  In-jun Hwang ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kwang-soo Seol ,  Sang-min Shin ,  Sang-moo Choi ,  Ju-hee Park

发明人： Sang-jin Park ,  In-jun Hwang ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kwang-soo Seol ,  Sang-min Shin ,  Sang-moo Choi ,  Ju-hee Park

IPC分类号： G11C16/04

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.

摘要翻译： 半导体存储器件可以包括半导体衬底，凹入半导体衬底中的控制栅电极，控制栅电极和半导体衬底之间的存储节点层，存储节点层和半导体衬底之间的隧穿绝缘层， 存储节点层和控制栅电极之间的绝缘层以及围绕控制栅电极并由一对相对的分隔绝缘层隔开的第一和第二沟道区。 操作半导体存储器件的方法可以包括通过阻塞绝缘层进行电荷隧穿而在存储节点层中编程数据，从而实现相对较高的可靠性和效率。

公开(公告)号：US20100008136A1

公开(公告)日：2010-01-14

申请号：US12458294

申请日：2009-07-08

申请人： Kwang-soo Seol ,  Sung-Il Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

发明人： Kwang-soo Seol ,  Sung-Il Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621

摘要： Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying a first pass voltage to non-selected memory cells closest to the selected memory cell of the cell string; applying a second pass voltage to second closest non-selected memory cells to the selected memory cell; and applying a third pass voltage to other non-selected memory cells, where the first pass voltage is less than each of the second and third pass voltages and the second pass voltage is greater than the third pass voltage.

摘要翻译： 提供了操作NAND非易失性存储器件的方法。 操作方法包括从单元串的多个存储单元中向所选存储单元施加读取电压或验证电压以验证或读取所选存储单元的编程状态; 对最靠近所述单元串的选定存储单元的未选择存储单元施加第一通过电压; 将第二通过电压施加到所选择的存储器单元的第二最近的未选择的存储器单元; 以及向其他未选择的存储单元施加第三通过电压，其中第一通过电压小于第二和第三通过电压中的每一个，并且第二通过电压大于第三通过电压。

公开(公告)号：US08379480B2

公开(公告)日：2013-02-19

申请号：US13370856

申请日：2012-02-10

申请人： Kwang-soo Seol ,  Yoon-dong Park ,  Suk-pil Kim

发明人： Kwang-soo Seol ,  Yoon-dong Park ,  Suk-pil Kim

IPC分类号： G11C8/00

CPC分类号： H01L29/7926 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/0688 ,  H01L27/11517 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/792

摘要： A multi-layered non-volatile memory device and a method of manufacturing the same. The non-volatile memory device may include a plurality of first semiconductor layers having a stack structure. A plurality of control gate electrodes may extend across the first semiconductor layers. A first body contact layer may extend across the first semiconductor layers. A plurality of charge storage layers may be interposed between the control gate electrodes and the first semiconductor layers.

公开(公告)号：US08053719B2

公开(公告)日：2011-11-08

申请号：US12385122

申请日：2009-03-31

申请人： Kwang-soo Seol ,  Yoon-dong Park

发明人： Kwang-soo Seol ,  Yoon-dong Park

IPC分类号： H01L31/00 ,  H01L27/00

CPC分类号： H01L27/14603 ,  H01L27/14627 ,  H01L27/307 ,  H01L51/0043 ,  H01L51/0073 ,  H01L51/424 ,  H01L51/4246 ,  Y02E10/549

摘要： Provided is an image sensor using a photo-detecting molecule and a method of operating the image sensor. The image sensor may include a plurality of first electrodes disposed parallel to each other and a plurality of second electrodes disposed parallel to each other in a direction perpendicular to the first electrodes and above the first electrodes, and a plurality of subpixels formed in regions where the first electrodes cross the second electrodes. Each of the subpixels may comprise a photo-detecting molecule layer that may generate charges by absorbing light having a certain wavelength, a charge generation layer that may form a plurality of secondary electrons by receiving the charges from the photo-detecting molecule layer when a known voltage is applied between the first electrodes and the second electrodes, and a variable resistance layer, an electrical state of which is changed by receiving the secondary electrons generated from the charge generation layer.

摘要翻译： 提供了使用光检测分子的图像传感器和操作图像传感器的方法。 图像传感器可以包括彼此平行设置的多个第一电极和在垂直于第一电极并且在第一电极上方彼此平行设置的多个第二电极，以及多个子像素，其形成在 第一电极与第二电极交叉。 每个子像素可以包括可以通过吸收具有一定波长的光而产生电荷的光检测分子层，电荷产生层可以通过从已知的光检测分子层接收电荷而形成多个二次电子 在第一电极和第二电极之间施加电压，并且通过接收从电荷产生层产生的二次电子而改变其电状态的可变电阻层。

公开(公告)号：US07995396B2

公开(公告)日：2011-08-09

申请号：US12458294

申请日：2009-07-08

申请人： Kwang-soo Seol ,  Sung-II Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

发明人： Kwang-soo Seol ,  Sung-II Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

IPC分类号： G11C11/34

CPC分类号： G11C16/3454 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621

摘要： Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying a first pass voltage to non-selected memory cells closest to the selected memory cell of the cell string; applying a second pass voltage to second closest non-selected memory cells to the selected memory cell; and applying a third pass voltage to other non-selected memory cells, where the first pass voltage is less than each of the second and third pass voltages and the second pass voltage is greater than the third pass voltage.

摘要翻译： 提供了操作NAND非易失性存储器件的方法。 操作方法包括从单元串的多个存储单元中向所选存储单元施加读取电压或验证电压以验证或读取所选存储单元的编程状态; 对最靠近所述单元串的选定存储单元的未选择存储单元施加第一通过电压; 将第二通过电压施加到所选择的存储器单元的第二最近的未选择的存储器单元; 以及向其他未选择的存储单元施加第三通过电压，其中第一通过电压小于第二和第三通过电压中的每一个，并且第二通过电压大于第三通过电压。

公开(公告)号：US08053302B2

公开(公告)日：2011-11-08

申请号：US12461416

申请日：2009-08-11

申请人： Kwang-soo Seol ,  Yoon-dong Park

发明人： Kwang-soo Seol ,  Yoon-dong Park

IPC分类号： H01L21/8239

CPC分类号： H01L27/11578 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： A non-volatile memory device and a method of manufacturing the non-volatile memory device are provided. At least one first semiconductor layer and at least one second semiconductor layer are disposed. At least one control gate electrode is disposed between the at least one first semiconductor layer and the at least one second semiconductor layer. At least one first layer selection line is capacitively coupled to the at least one first semiconductor layer. At least one second layer selection line is capacitively coupled to the at least one second semiconductor layer.

摘要翻译： 提供了一种非易失性存储器件和制造该非易失性存储器件的方法。 设置至少一个第一半导体层和至少一个第二半导体层。 至少一个控制栅电极设置在至少一个第一半导体层和至少一个第二半导体层之间。 至少一个第一层选择线电容耦合到至少一个第一半导体层。 至少一个第二层选择线电容耦合到至少一个第二半导体层。

公开(公告)号：US20090244980A1

公开(公告)日：2009-10-01

申请号：US12382790

申请日：2009-03-24

申请人： Kwang-soo Seol ,  Young-gu Jin ,  Yoon-dong Park

发明人： Kwang-soo Seol ,  Young-gu Jin ,  Yoon-dong Park

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3454

摘要： Provided is a method and device for reducing lateral movement of charges. The method may include pre-programming at least one memory cell that is in an erased state by applying a pre-programming voltage to the at least one memory cell to have a narrower distribution of threshold voltages than the at least one erased state memory cell and verifying that the pre-programmed memory cell is in the pre-programmed state using a negative effective verifying voltage.

摘要翻译： 提供一种用于减少电荷的横向移动的方法和装置。 该方法可以包括通过对至少一个存储器单元施加预编程电压以使得具有比所述至少一个擦除状态存储器单元更窄的阈值电压分布来对处于擦除状态的至少一个存储器单元进行预编程，以及 使用负的有效验证电压来验证预编程存储器单元是否处于预编程状态。