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    Semiconductor memory device including recessed control gate electrode
    3.
    发明授权
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US07732855B2

    公开(公告)日：2010-06-08

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L21/28

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    Semiconductor memory device including recessed control gate electrode
    4.
    发明申请
    Semiconductor memory device including recessed control gate electrode 失效
    半导体存储器件包括凹入控制栅电极

    公开(公告)号：US20080093662A1

    公开(公告)日：2008-04-24

    申请号：US11808982

    申请日：2007-06-14

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Yoon-dong Park ,  Sang-min Shin ,  In-jun Hwang ,  Sang-moo Choi ,  Ju-hee Park

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42324 ,  G11C16/0408 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42336 ,  H01L29/4234 ,  H01L29/42352 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

    摘要： A semiconductor memory device may include a semiconductor substrate, at least one control gate electrode, at least one storage node layer, at least one tunneling insulating layer, at least one blocking insulating layer, and/or first and second channel regions. The at least one control gate electrode may be recessed into the semiconductor substrate. The at least one storage node layer may be between a sidewall of the at least one control gate electrode and the semiconductor substrate. The at least one tunneling insulating layer may be between the at least one storage node layer and the at least one control gate electrode. The at least one blocking insulating layer may be between the storage node layer and the control gate electrode. The first and second channel regions may be between the at least one tunneling insulating layer and the semiconductor substrate to surround at least a portion of the sidewall of the control gate electrode and/or may be separated from each other.

    摘要翻译： 半导体存储器件可以包括半导体衬底，至少一个控制栅电极，至少一个存储节点层，至少一个隧道绝缘层，至少一个阻挡绝缘层和/或第一和第二沟道区。 至少一个控制栅电极可以凹进到半导体衬底中。 所述至少一个存储节点层可以在所述至少一个控制栅电极的侧壁和所述半导体衬底之间。 所述至少一个隧道绝缘层可以在所述至少一个存储节点层和所述至少一个控制栅电极之间。 所述至少一个阻挡绝缘层可以在所述存储节点层和所述控制栅电极之间。 第一和第二沟道区可以在至少一个隧道绝缘层和半导体衬底之间，以围绕控制栅电极的侧壁的至少一部分和/或可以彼此分离。

    Charge trap memory device
    6.
    发明申请
    Charge trap memory device 审中-公开
    电荷陷阱记忆装置

    公开(公告)号：US20080087944A1

    公开(公告)日：2008-04-17

    申请号：US11905769

    申请日：2007-10-04

    申请人： Sang-min Shin ,  Kwang-soo Seol ,  Sang-Jin Park ,  Jung-hun Sung ,  Sang-moo Choi

    发明人： Sang-min Shin ,  Kwang-soo Seol ,  Sang-Jin Park ,  Jung-hun Sung ,  Sang-moo Choi

    IPC分类号： H01L29/792

    CPC分类号： H01L29/42332 ,  H01L29/40114

    摘要： A charge trap memory device may include a tunnel insulating layer formed on a substrate. A charge trap layer may be formed on the tunnel insulating layer, wherein the charge trap layer is a higher-k dielectric insulating layer doped with one or more transition metals. The tunneling insulating layer may be relatively non-reactive with respect to metals in the charge trap layer. The tunneling insulating layer may also reduce or prevent metals in the charge trap layer from diffusing into the substrate.

    摘要翻译： 电荷陷阱存储器件可以包括形成在衬底上的隧道绝缘层。 电荷陷阱层可以形成在隧道绝缘层上，其中电荷陷阱层是掺杂有一种或多种过渡金属的较高k介电绝缘层。 隧穿绝缘层相对于电荷陷阱层中的金属可能是相对不反应的。 隧道绝缘层还可以减少或防止电荷陷阱层中的金属扩散到衬底中。

    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers
    7.
    发明授权
    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers 失效
    非易失性存储器件及其编程方法，包括通过电荷陷阱层之间的衬垫氧化物层移动电子

    公开(公告)号：US07668016B2

    公开(公告)日：2010-02-23

    申请号：US12078141

    申请日：2008-03-27

    申请人： Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    发明人： Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/7923

    摘要： Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

    摘要翻译： 提供非易失性存储器件以及通过衬垫氧化物层对电子在电荷陷阱层之间移动的非易失性存储器件进行编程的方法。 非易失性存储器件包括半导体衬底上的电荷陷阱层，并且存储电子，在第一电荷陷阱层上形成焊盘氧化物层，并且在焊盘氧化物层上存储第二陷阱层并存储电子。 在写入数据的编程模式中，所存储的电子在第一电荷陷阱层的第一位置和第二电荷陷阱层的第一位置之间通过焊盘氧化物层或第一电荷陷阱的第二位置之间移动 层和第二电荷陷阱层的第二位置穿过衬垫氧化物层。

    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers
    8.
    发明申请
    Non-volatile memory devices and programming methods thereof including moving electrons through pad oxide layers between charge trap layers 失效
    非易失性存储器件及其编程方法，包括通过电荷陷阱层之间的衬垫氧化物层移动电子

    公开(公告)号：US20090034341A1

    公开(公告)日：2009-02-05

    申请号：US12078141

    申请日：2008-03-27

    申请人： Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    发明人： Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park ,  Sang-moo Choi

    IPC分类号： G11C16/04 ,  H01L29/792

    CPC分类号： G11C16/0475 ,  G11C16/10 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/7923

    摘要： Non-volatile memory devices and methods of programming a non-volatile memory device in which electrons are moved between charge trap layers through a pad oxide layer are provided. The non-volatile memory devices include a charge trap layer on a semiconductor substrate and storing electrons, a pad oxide layer on the first charge trap layer, and a second trap layer on the pad oxide layer and storing electrons. In a programming mode in which data is written, the stored electrons are moved between a first position of the first charge trap layer and a first position of the second charge trap layer through the pad oxide layer or between a second position of the first charge trap layer and a second position of the second charge trap layer through the pad oxide layer.

    摘要翻译： 提供非易失性存储器件以及通过衬垫氧化物层对电子在电荷陷阱层之间移动的非易失性存储器件进行编程的方法。 非易失性存储器件包括半导体衬底上的电荷陷阱层，并且存储电子，在第一电荷陷阱层上形成焊盘氧化物层，并且在焊盘氧化物层上存储第二陷阱层并存储电子。 在写入数据的编程模式中，所存储的电子在第一电荷陷阱层的第一位置和第二电荷陷阱层的第一位置之间通过焊盘氧化物层或第一电荷陷阱的第二位置之间移动 层和第二电荷陷阱层的第二位置穿过衬垫氧化物层。

    Method of programming nonvolatile memory device
    10.
    发明授权
    Method of programming nonvolatile memory device 有权
    非易失性存储器件编程方法

    公开(公告)号：US07760551B2

    公开(公告)日：2010-07-20

    申请号：US12232082

    申请日：2008-09-10

    申请人： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

    发明人： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C16/3454 ,  G11C16/3486

    摘要： A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.

    摘要翻译： 非易失性存储器件的编程方法可以包括将程序电压施加到存储单元。 补充脉冲可以施加到存储器单元，以便在施加编程电压之后促进电荷的热化。 在施加补充脉冲之后，可以将复原电压施加到存储单元。 可以在施加恢复电压之后使用验证电压来验证存储器单元的编程状态。