公开(公告)号：US07951712B2

公开(公告)日：2011-05-31

申请号：US12556094

申请日：2009-09-09

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US20100003814A1

公开(公告)日：2010-01-07

申请号：US12556094

申请日：2009-09-09

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/768

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07605472B2

公开(公告)日：2009-10-20

申请号：US11706885

申请日：2007-02-15

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US20070138642A1

公开(公告)日：2007-06-21

申请号：US11706885

申请日：2007-02-15

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

摘要翻译： 提供了包括封盖层和形成互连的方法的半导体器件的互连。 半导体器件的互连是铜镶嵌互连，其中覆盖层形成为通过化学机械抛光（CMP）处理的铜层上的氮化硅层和碳化硅层的双层。 因此，可以在提供优异的泄漏抑制的同时保持碳化硅层的高蚀刻选择性和低介电常数。

公开(公告)号：US07205666B2

公开(公告)日：2007-04-17

申请号：US11367790

申请日：2006-03-03

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US20060163736A1

公开(公告)日：2006-07-27

申请号：US11367790

申请日：2006-03-03

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US07037835B2

公开(公告)日：2006-05-02

申请号：US10744277

申请日：2003-12-23

申请人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

发明人： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC分类号： H01L21/44

CPC分类号： H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US20100001186A1

公开(公告)日：2010-01-07

申请号：US12483997

申请日：2009-06-12

申请人： Soon-sik HWANG ,  Byung-sam Choi ,  Ki-chul Park

发明人： Soon-sik HWANG ,  Byung-sam Choi ,  Ki-chul Park

IPC分类号： G01N23/04

CPC分类号： H01J37/153 ,  H01J37/21 ,  H01J37/265 ,  H01J2237/1534 ,  H01J2237/216 ,  H01J2237/2826

摘要： A method of measuring a dimension of a measurement pattern by using a scanning electron microscope is provided. The method of measuring the dimension of the pattern includes: (a) moving to a correction pattern that is adjacent to the measurement pattern. The correction pattern comprises circular patterns to correct focus and/or stigmatism of the scanning electron microscope with respect to the correction pattern. The method further includes (b) measuring the dimension of the measurement pattern under measurement conditions to which the corrected focus and/or the stigmatism are reflected.

摘要翻译： 提供了通过使用扫描电子显微镜测量测量图案的尺寸的方法。 测量图案的尺寸的方法包括：（a）移动到与测量图案相邻的校正图案。 校正图案包括用于校正扫描电子显微镜相对于校正图案的焦点和/或斑点的圆形图案。 该方法还包括（b）在校正的焦点和/或标志被反映的测量条件下测量测量图案的尺寸。

公开(公告)号：US07928002B2

公开(公告)日：2011-04-19

申请号：US12396632

申请日：2009-03-03

申请人： Mu-kyeng Jung ,  Sun-jung Lee ,  Ki-chul Park

发明人： Mu-kyeng Jung ,  Sun-jung Lee ,  Ki-chul Park

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.

摘要翻译： 一种形成半导体器件的布线层的方法，包括形成第一层间绝缘层，以具有对应于待形成在支撑层上的层间绝缘层的厚度的一部分的第一厚度并形成第一接触 插入第一层间绝缘层。 该方法还包括在第一接触插塞和第一层间绝缘层上形成具有第二厚度的第二层间绝缘层，从而形成层间绝缘层，其中第二厚度对应于层间绝缘层的其余厚度 并且形成与所述第二层间绝缘层中的所述第一接触插塞连接的第二接触插塞，由此形成包括所述第一接触插塞和所述第二接触插塞的局部布线层。