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    Memory Cells
    2.
    发明申请
    Memory Cells 有权
    记忆细胞

    公开(公告)号：US20110133268A1

    公开(公告)日：2011-06-09

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

    Memory cells containing charge-trapping zones
    4.
    发明授权
    Memory cells containing charge-trapping zones 有权
    含有电荷捕获区的存储单元

    公开(公告)号：US08228743B2

    公开(公告)日：2012-07-24

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A Weimer ,  Arup Bhattacharyya

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

    HIGH-K TRILAYER DIELECTRIC DEVICE AND METHODS
    6.
    发明申请
    HIGH-K TRILAYER DIELECTRIC DEVICE AND METHODS 审中-公开
    高K系列电介质器件及方法

    公开(公告)号：US20080237683A1

    公开(公告)日：2008-10-02

    申请号：US11694059

    申请日：2007-03-30

    申请人： Kyu S. Min ,  Thomas M. Graettinger

    发明人： Kyu S. Min ,  Thomas M. Graettinger

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/42324 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/3144 ,  H01L21/3145 ,  H01L21/3162 ,  H01L29/513 ,  H01L29/7881

    摘要： Methods and structures are described for reducing a gate leakage current and increasing gate coupling ratio in a semiconductor device. In some embodiments, nitride layers are used to limit the oxidation of adjacent silicon gate regions due to oxygen in an intermediate insulator. In various embodiments, the intermediate insulator includes a high-κ dielectric material. Apparatus according to embodiments of the invention are also disclosed.

    摘要翻译： 描述了用于减小半导体器件中的栅极漏电流和增加栅极耦合比的方法和结构。 在一些实施例中，由于中间绝缘体中的氧，氮化物层用于限制相邻硅栅极区域的氧化。 在各种实施例中，中间绝缘体包括高k电介质材料。 还公开了根据本发明的实施例的设备。

    Nanocrystal formation using atomic layer deposition and resulting apparatus
    7.
    发明授权
    Nanocrystal formation using atomic layer deposition and resulting apparatus 有权
    使用原子层沉积和所得装置的纳米晶体形成

    公开(公告)号：US08643079B2

    公开(公告)日：2014-02-04

    申请号：US12115192

    申请日：2008-05-05

    申请人： Prashant Majhi ,  Kyu S. Min ,  Wilman Tsai

    发明人： Prashant Majhi ,  Kyu S. Min ,  Wilman Tsai

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/0262 ,  H01L21/3141 ,  H01L29/42324

    摘要： Nanocrystal structures formed using atomic layer deposition (ALD) processes are useful in the formation of integrated circuits such as memory devices. Rather than continuing the ALD process until a continuous layer is formed, the ALD process is halted prematurely to leave a discontinuous formation of nanocrystals which are then capped by a different material, thus forming a layer with a discontinuous portion and a bulk portion. Such nanocrystals can serve as charge-storage sites within the bulk portion, and the resulting structure can serve as a floating gate of a floating-gate memory cell. A floating gate may contain one or more layers of such nanocrystal structures.

    摘要翻译： 使用原子层沉积（ALD）工艺形成的纳米晶体结构在形成诸如存储器件的集成电路中是有用的。 不是继续ALD过程直到形成连续层，所以ALD过程被过早地停止以留下不连续的纳米晶体形成，然后被不同的材料覆盖，从而形成具有不连续部分和主体部分的层。 这种纳米晶体可以用作体积部分内的电荷存储位置，并且所得结构可以用作浮栅存储器单元的浮置栅极。 浮动栅极可以包含一层或多层这样的纳米晶体结构。

    Memory cells, methods of forming dielectric materials, and methods of forming memory cells
    8.
    发明授权
    Memory cells, methods of forming dielectric materials, and methods of forming memory cells 有权
    记忆单元，介电材料的形成方法以及形成记忆单元的方法

    公开(公告)号：US08183110B2

    公开(公告)日：2012-05-22

    申请号：US13116401

    申请日：2011-05-26

    申请人： D. V. Nirmal Ramaswamy ,  Noel Rocklein ,  Kyu S. Min

    发明人： D. V. Nirmal Ramaswamy ,  Noel Rocklein ,  Kyu S. Min

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

    摘要： Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

    摘要翻译： 一些实施例包括存储器单元。 存储单元可以包括隧道电介质材料，隧道电介质材料上方的电荷保持区域，电荷保持区域上的结晶超高k电介质材料，以及结晶超高k电介质材料上的控制栅极材料。 此外，存储器单元可以包括电荷保持区域和结晶超高k电介质材料之间的非晶区域，和/或可以包括晶体超高k电介质材料和控制栅极材料之间的非晶区域。 一些实施例包括形成在电荷保持区域和结晶超高k电介质材料之间形成非晶区域的存储单元的方法，和/或在晶体超高k电介质材料和控制栅极之间包含非晶区域的方法 材料。

    SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME
    10.
    发明申请
    SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME 有权
    用于非挥发性数据存储的自对准电荷捕获层，其形成方法和包含其的装置

    公开(公告)号：US20080237691A1

    公开(公告)日：2008-10-02

    申请号：US11693925

    申请日：2007-03-30

    申请人： Kyu S. Min

    发明人： Kyu S. Min

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/788 ,  H01L21/76224 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L29/0649 ,  H01L29/42332 ,  H01L29/7881

    摘要： A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.

    摘要翻译： 离散存储元件膜设置在隧道电介质膜上方，抵靠浅沟槽隔离结构，并且在条件下，在浅沟槽隔离结构的垂直曝光时抵抗离散存储元件膜的形成。 离散存储元件膜也设置在隧道电介质膜上方抵靠凹陷隔离结构。 微电子器件结合了离散存储元件膜。 计算系统结合了微电子器件。