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    Memory Cells
    2.
    发明申请
    Memory Cells 有权
    记忆细胞

    公开(公告)号：US20110133268A1

    公开(公告)日：2011-06-09

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

    Capacitor structures with oxynitride layer between capacitor plate and capacitor dielectric layer
    6.
    发明授权
    Capacitor structures with oxynitride layer between capacitor plate and capacitor dielectric layer 有权
    在电容器板和电容器介质层之间具有氧氮化物层的电容器结构

    公开(公告)号：US07489000B2

    公开(公告)日：2009-02-10

    申请号：US11358647

    申请日：2006-02-21

    申请人： Ronald A. Weimer

    发明人： Ronald A. Weimer

    IPC分类号： H01L29/94

    CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02183 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/0805 ,  H01L28/56 ,  H01L28/84

    摘要： Methods for fuming dielectric layers over polysilicon substrates, useful in the construction of capacitors and other semiconductor circuit components are provided. A self-limiting nitric oxide (NO) anneal of a polysilicon layer such as an HSG polysilicon capacitor electrode, at less than 800° C., is utilized to grow a thin oxide (oxynitride) layer of about 40 angstroms or less over the polysilicon layer. The NO anneal provides a nitrogen layer at the polysilicon-oxide interface that limits further oxidation of the polysilicon layer and growth of the oxide layer. The oxide layer is exposed to a nitrogen-containing gas to nitridize the surface of the oxide layer and reduce the effective dielectric constant of the oxide layer. The process is particularly useful in forming high K dielectric insulating layers such as tantalum pentoxide over polysilicon. The nitridized oxynitride layer inhibits oxidation of the underlying polysilicon layer in a post-treatment oxidizing anneal of the high K dielectric, thus maintaining the oxide layer as a thin layer over the polysilicon layer.

    摘要翻译： 提供了在多晶硅衬底上形成电介质层的方法，其用于构建电容器和其它半导体电路部件。 利用多晶硅层（例如HSG多晶硅电容器电极）在小于800℃下的自限制性一氧化氮（NO）退火，以在多晶硅上生长约40埃或更少的薄氧化物（氧氮化物）层 层。 NO退火在多晶硅 - 氧化物界面处提供氮层，限制多晶硅层的进一步氧化和氧化物层的生长。 将氧化物层暴露于含氮气体中以氮化氧化物层的表面并降低氧化物层的有效介电常数。 该方法特别适用于在多晶硅上形成高K电介质绝缘层，例如五氧化二钽。 氮化氮氧化物层在高K电介质的后处理氧化退火中抑制下面的多晶硅层的氧化，从而将氧化物层保持在多晶硅层上的薄层。

    Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces
    8.
    发明授权
    Microfeature workpiece processing apparatus and methods for batch deposition of materials on microfeature workpieces 失效
    微型工件加工设备和微型工件上批量堆放材料的微型工件加工设备及方法

    公开(公告)号：US07235138B2

    公开(公告)日：2007-06-26

    申请号：US10646607

    申请日：2003-08-21

    申请人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

    发明人： Lingyi A. Zheng ,  Trung T. Doan ,  Lyle D. Breiner ,  Er-Xuan Ping ,  Ronald A. Weimer ,  David J. Kubista ,  Kevin L. Beaman ,  Cem Basceri

    IPC分类号： C23C16/00 ,  H01L21/306 ,  C23F1/00

    CPC分类号： C23C16/4583 ,  C23C16/45546 ,  C23C16/45578 ,  Y10S206/832

    摘要： The present disclosure describes apparatus and methods for processing microfeature workpieces, e.g., by depositing material on a microelectronic semiconductor using atomic layer deposition. Some of these apparatus include microfeature workpiece holders that include gas distributors. One exemplary implementation provides a microfeature workpiece holder adapted to hold a plurality of microfeature workpieces. This workpiece holder includes a plurality of workpiece supports and a gas distributor. The workpiece supports are adapted to support a plurality of microfeature workpieces in a spaced-apart relationship to define a process space adjacent a surface of each microfeature workpiece. The gas distributor includes an inlet and a plurality of outlets, with each of the outlets positioned to direct a flow of process gas into one of the process spaces.

    摘要翻译： 本公开描述了用于处理微特征工件的装置和方法，例如通过使用原子层沉积在微电子半导体上沉积材料。 这些设备中的一些包括微型工件保持器，其包括气体分配器。 一个示例性实施例提供了适于保持多个微特征工件的微特征工件保持器。 该工件保持器包括多个工件支撑件和气体分配器。 工件支撑件适于以间隔的关系支撑多个微特征工件以限定与每个微特征工件的表面相邻的工艺空间。 气体分配器包括入口和多个出口，其中每个出口被定位成将处理气体流引导到处理空间中的一个中。

    Double sided container process used during the manufacture of a semiconductor device
    9.
    发明授权
    Double sided container process used during the manufacture of a semiconductor device 有权
    在制造半导体器件期间使用的双面容器工艺

    公开(公告)号：US07084448B2

    公开(公告)日：2006-08-01

    申请号：US10786348

    申请日：2004-02-24

    申请人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

    发明人： Scott J. DeBoer ,  Ronald A. Weimer ,  John T. Moore

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10888 ,  H01L21/76831 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91 ,  H01L29/41725

    摘要： A method used during the formation of a semiconductor device comprises providing a wafer substrate assembly comprising a plurality of digit line plug contact pads and capacitor storage cell contact pads which contact a semiconductor wafer. A dielectric layer is provided over the wafer substrate assembly and etched to expose the digit line plug contact pads, and a liner is provided in the opening. A portion of the digit line plug is formed, then the dielectric layer is etched again to expose the capacitor storage cell contact pads. A capacitor bottom plate is formed to contact the storage cell contact pads, then the dielectric layer is etched a third time using the liner and the bottom plate as an etch stop layer. A capacitor cell dielectric layer and capacitor top plate are formed which provide a double-sided container cell. An additional dielectric layer is formed, then the additional dielectric layer, cell top plate, and the cell dielectric are etched to expose the digit line plug portion. Finally, a second digit line plug portion is formed to contact the first plug portion. A novel structure resulting from the inventive method is also discussed.

    摘要翻译： 在形成半导体器件期间使用的方法包括提供晶片衬底组件，其包括接触半导体晶片的多个数字线插头接触焊盘和电容器存储单元接触焊盘。 电介质层设置在晶片衬底组件上并被蚀刻以暴露数字线插头接触垫，并且衬套设置在开口中。 形成数字线插头的一部分，然后再次蚀刻电介质层以暴露电容器存储单元接触垫。 电容器底板形成为与存储单元接触焊盘接触，然后使用衬垫和底板作为蚀刻停止层，第三次蚀刻电介质层。 形成电容器单元电介质层和电容器顶板，其提供双面容器单元。 形成附加的电介质层，然后蚀刻附加的电介质层，电池顶板和电池电介质以露出数字线插头部分。 最后，形成第二数字线插头部分以接触第一插头部分。 还讨论了由本发明方法产生的新颖结构。