公开(公告)号：US20060284302A1

公开(公告)日：2006-12-21

申请号：US11447943

申请日：2006-06-07

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： H01L23/52

CPC分类号： H01L23/58 ,  H01L23/5286 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/83801 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.

摘要翻译： 提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。 半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。

公开(公告)号：US08093075B2

公开(公告)日：2012-01-10

申请号：US12656134

申请日：2010-01-19

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： H01L21/00

CPC分类号： H01L23/58 ,  H01L23/5286 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/83801 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.

摘要翻译： 提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。 半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。

公开(公告)号：US20100123216A1

公开(公告)日：2010-05-20

申请号：US12656134

申请日：2010-01-19

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L23/58 ,  H01L23/5286 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/83801 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.

摘要翻译： 提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。 半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。

公开(公告)号：US07675158B2

公开(公告)日：2010-03-09

申请号：US11447943

申请日：2006-06-07

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： H01L23/52 ,  H01L27/04 ,  H01L23/373 ,  H01L21/822

CPC分类号： H01L23/58 ,  H01L23/5286 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/83801 ,  H01L2924/01068 ,  H01L2924/14 ,  H01L2924/19104 ,  H01L2924/00014 ,  H01L2924/00

摘要： Provided are a semiconductor integrated circuit including a power supply, a semiconductor system including the semiconductor integrated circuit, and a method of forming the semiconductor integrated circuit. The semiconductor integrated circuit includes: a semiconductor substrate on a surface of which a plurality of electrical circuits and a plurality of power pads are mounted; an insulation layer stacked on the semiconductor substrate; a first conductive layer connected to a first power pad by a first via and stacked on the insulation layer; a second conductive layer connected to a second power pad by a second via, stacked on the insulation layer, and separated from the first insulation layer; and a power generation layer stacked on the first conductive layer and the second conductive layer and that generates voltage.

摘要翻译： 提供了包括电源，包括半导体集成电路的半导体系统和形成半导体集成电路的方法的半导体集成电路。 半导体集成电路包括：表面上安装有多个电路和多个电源焊盘的半导体衬底; 层叠在所述半导体基板上的绝缘层; 第一导电层，其通过第一通孔连接到第一功率垫并堆叠在所述绝缘层上; 通过第二通孔连接到第二功率垫的第二导电层，堆叠在绝缘层上并与第一绝缘层分离; 以及堆叠在第一导电层和第二导电层上并产生电压的发电层。

公开(公告)号：US07336554B2

公开(公告)日：2008-02-26

申请号：US11258565

申请日：2005-10-25

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C5/066 ,  H04Q2213/13103 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to an internal portion and serial converting parallel data applied from the internal portion and outputting the serial converted data to the IO circuit.

摘要翻译： 一种半导体存储器件包括用于接收或输出串行化的命令信号，地址信号和数据的IO电路，以及用于并行转换串行化命令信号的IO信号控制电路，地址信号和通过IO电路输入的数据并且将并行转换 发送到内部部分，并串行转换从内部部分应用的并行数据，并将串行转换数据输出到IO电路。

公开(公告)号：US20060120359A1

公开(公告)日：2006-06-08

申请号：US11258565

申请日：2005-10-25

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： H04L12/50 ,  H04Q11/00

CPC分类号： G11C5/066 ,  H04Q2213/13103 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to an internal portion and serial converting parallel data applied from the internal portion and outputting the serial converted data to the IO circuit.

摘要翻译： 一种半导体存储器件包括用于接收或输出串行化的命令信号，地址信号和数据的IO电路，以及用于并行转换串行化命令信号的IO信号控制电路，地址信号和通过IO电路输入的数据并且将并行转换 发送到内部部分，并串行转换从内部部分应用的并行数据，并将串行转换数据输出到IO电路。

公开(公告)号：US09076770B2

公开(公告)日：2015-07-07

申请号：US13569267

申请日：2012-08-08

申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

IPC分类号： H01L23/48 ,  H01L23/525 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

CPC分类号： H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上吹入保险丝来个性化， 将先前通过熔断保险丝连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

公开(公告)号：US08756475B2

公开(公告)日：2014-06-17

申请号：US12929250

申请日：2011-01-11

申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

IPC分类号： H03M13/00 ,  H03M13/29 ,  G06F11/08

CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

公开(公告)号：US07212052B2

公开(公告)日：2007-05-01

申请号：US10925522

申请日：2004-08-25

申请人： Kyu-Hyoun Kim

发明人： Kyu-Hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.

摘要翻译： 提供延迟锁定环路电路，其包括产生延迟锁定环路输出信号的延迟锁定环路和抖动抑制器。 抖动抑制器可以包括延迟电路，其接收延迟锁定环路输出信号并产生延迟锁定环路输出信号的一个或多个延迟版本;以及相位插值器，其接收延迟锁定环路输出信号和一个或多个延迟锁定环路输出信号 延迟锁定环路输出信号。 在本发明的某些实施例中，延迟电路可以包括多个串联连接的延迟单元。 这些延迟单元中的每一个可以在等于输入到延迟锁定环路的外部时钟信号的一个时钟周期的时间延迟输入的信号。

公开(公告)号：US20050122149A1

公开(公告)日：2005-06-09

申请号：US11005821

申请日：2004-12-07

申请人： Geun-Hee Cho ,  Kyu-Hyoun Kim

发明人： Geun-Hee Cho ,  Kyu-Hyoun Kim

IPC分类号： G11C8/00 ,  H03K5/04 ,  H03K5/135 ,  H03K5/151 ,  H03K5/156 ,  H03L7/081

CPC分类号： H03K5/151 ,  H03K5/135 ,  H03K5/1565 ,  H03L7/0812

摘要： Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.

摘要翻译： 延迟锁定环集成电路包括占空比校正电路。 该占空比校正电路响应于具有不均匀占空比的至少一个输入时钟信号而产生具有基本均匀的占空比的至少一个输出时钟信号。 占空比校正电路还响应于在占空比校正电路内同步省电占空比更新操作的定时的待机控制信号。 这些更新操作重置校正电路的设定点。