公开(公告)号：US20160211885A1

公开(公告)日：2016-07-21

申请号：US14381019

申请日：2013-03-14

Applicant: LSI Corporation

Inventor： Donald R. Laturell ,  Said E. Abdelli ,  Peter Kiss ,  James F. MacDonald ,  Ross S. Wilson

IPC: H04B3/02 ,  H04B15/00

CPC classification number: H04B3/02 ,  G06G7/14 ,  H04B15/00

Abstract: A circuit for combining analog signals includes first and second bitstream generators and a directional coupled connected therewith. The first bitstream generator receives a first analog signal and generates a first digital bitstream as a function thereof. The second bitstream generator receives a second analog signal and generates a second digital bitstream as a function thereof. The first and second bitstream generators are configured to maintain a ninety-degree phase difference between the first and second digital bitstreams. The directional coupler receives, at a first port, the first digital bitstream, and receives, at a second port, the second digital bitstream. The directional coupler includes a third port that is terminated, and a fourth port which generates a first output signal indicative of a combination of the first and second digital bitstreams in a manner that an image component is suppressed without a need for filtering.

Abstract translation: 用于组合模拟信号的电路包括第一和第二比特流发生器和与之相连的定向耦合。 第一比特流发生器接收第一模拟信号并产生第一数字比特流作为其功能。 第二比特流发生器接收第二模拟信号并产生第二数字比特流作为其功能。 第一和第二比特流发生器被配置为保持第一和第二数字比特流之间的九十度的相位差。 定向耦合器在第一端口处接收第一数字比特流，并在第二端口接收第二数字比特流。 定向耦合器包括端接的第三端口，以及第四端口，其产生指示第一和第二数字位流的组合的第一输出信号，以使图像分量被抑制而不需要滤波。

公开(公告)号：US20160056848A1

公开(公告)日：2016-02-25

申请号：US14380936

申请日：2013-03-15

Applicant: LSI Corporation

Inventor： Peter Kiss ,  Said E. Abdelli ,  Donald R. Laturell ,  James F. MacDonald ,  Steven C. Pinault ,  Ross S. Wilson

IPC: H04B1/04 ,  H04L27/02

CPC classification number: H04B1/0475 ,  H03C1/52 ,  H03C1/60 ,  H03F3/24 ,  H04B1/68 ,  H04B2001/0408 ,  H04L27/02 ,  H04L27/06 ,  H04L27/063

Abstract: An SSB transmitter includes a digital-to-digital converter generating first and second real signal components as a function of a complex input signal supplied to the transmitter, and a digital Hilbert transformation module coupled with the digital-to-digital converter and operative to generate first and second transformed signals as a function of the first and second real signal components. The transmitter further includes first and second bit-stream generators operative to generate first and second analog signals as a function of the first and second transformed signals, respectively. The transmitter includes first and second amplifiers. The first amplifier is operative to generate a first amplified signal as a function of the first analog signal. The second amplifier is operative to generate a second amplified signal as a function of the second analog signal. An analog hybrid coupler is connected with the first and second amplifiers and operative to perform an analog Hilbert transformation.

Abstract translation: SSB发射机包括数字 - 数字转换器，其产生作为提供给发射机的复合输入信号的函数的第一和第二实信号分量;以及数字希尔伯特变换模块，与数字 - 数字转换器耦合并且可操作以产生 第一和第二变换信号作为第一和第二实信号分量的函数。 发射机还包括第一和第二比特流发生器，用于分别产生作为第一和第二变换信号的函数的第一和第二模拟信号。 发射机包括第一和第二放大器。 第一放大器用于产生作为第一模拟信号的函数的第一放大信号。 第二放大器用于产生作为第二模拟信号的函数的第二放大信号。 模拟混合耦合器与第一和第二放大器连接并且可操作以执行模拟希尔伯特变换。

公开(公告)号：US20150318030A1

公开(公告)日：2015-11-05

申请号：US14267344

申请日：2014-05-01

Applicant: LSI Corporation

Inventor： Ross S. Wilson ,  David W. Kelly ,  Daniel J. Dolan ,  Richard Rauschmayer

IPC: G11C7/10

CPC classification number: G06F3/06 ,  G06F13/4273 ,  G11C7/1072

Abstract: A method is provided, for example, to implement multiplexed communication between a controller and a preamplifier in a storage device. For example, multiplexed communication is implemented by controlling a bidirectional serial data line of a digital bus to selectively transmit digital signals in either a first direction from the controller to the preamplifier or a second direction from the preamplifier to the controller, in response to a direction control signal, and concurrently transmitting a synchronous clock signal over a clock signal line of the digital bus from the controller to the preamplifier to synchronize transfer and processing of the digital signals transmitted on the bidirectional serial data line of the digital bus. The direction control signal is transmitted from the controller to the preamplifier on one of the bidirectional serial data line and the clock signal line of the digital bus.

Abstract translation: 例如，提供了一种在存储设备中实现控制器与前置放大器之间的多路复用通信的方法。 例如，通过控制数字总线的双向串行数据线来实现多路复用通信，以响应于方向选择性地将从控制器的第一方向到前置放大器的数字信号或从前置放大器到控制器的第二方向 控制信号，同时通过数字总线的时钟信号线从控制器向前置放大器发送同步时钟信号，以同步数字总线双向串行数据线上发送的数字信号的传送和处理。 方向控制信号在双向串行数据线和数字总线的时钟信号线之一上从控制器发送到前置放大器。

公开(公告)号：US09078352B2

公开(公告)日：2015-07-07

申请号：US13662659

申请日：2012-10-29

Applicant: LSI Corporation

Inventor： Donald R. Laturell ,  Said E. Abdelli ,  Peter Kiss ,  James F. MacDonald ,  Ross S. Wilson

IPC: H05K1/00 ,  H05K3/30 ,  H05K1/02 ,  H01L23/498 ,  H05K3/46

CPC classification number: H05K1/0216 ,  H01L23/4985 ,  H01L23/5387 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/028 ,  H05K3/306 ,  H05K3/4691 ,  H05K2201/042 ,  Y10T29/4913 ,  H01L2924/00

Abstract: A electronic circuit with low inductance connections is disclosed. The electronic circuit includes a ground plane and a flex circuit. The flex circuit having a first surface generally facing the ground plane and a second surface opposite to the first surface. The flex circuit also having a flexible bridge defined thereof. The electronic circuit further includes a first electronic device communicatively coupled to the second surface of the flex circuit, a second electronic device communicatively coupled to the second surface of the flex circuit, and at least one conductive trace defined on the second surface of the flex circuit and extending along the flexible bridge. One end of the at least one conductive trace is configured for receiving an outbound current from the first electronic device and another end of the at least one conductive trace is communicatively coupled to the second electronic device through a vertical interconnect access.

Abstract translation: 公开了具有低电感连接的电子电路。 电子电路包括接地平面和柔性电路。 柔性电路具有大致面向接地平面的第一表面和与第一表面相对的第二表面。 柔性电路还具有由其限定的柔性桥。 电子电路还包括通信地耦合到柔性电路的第二表面的第一电子设备，通信地耦合到柔性电路的第二表面的第二电子设备，以及限定在柔性电路的第二表面上的至少一个导电迹线 并沿柔性桥延伸。 所述至少一个导电迹线的一端被配置为用于从所述第一电子器件接收出站电流，并且所述至少一个导电迹线的另一端通过垂直互连接入通信地耦合到所述第二电子器件。

公开(公告)号：US20140266820A1

公开(公告)日：2014-09-18

申请号：US14184334

申请日：2014-02-19

Applicant: LSI Corporation

Inventor： Peter Kiss ,  Said E. Abdelli ,  Donald R. Laturell ,  Ross S. Wilson ,  James F. MacDonald

IPC: H03M9/00

CPC classification number: H03M9/00 ,  H03F3/217 ,  H03F2200/331 ,  H03H17/0018 ,  H03H17/0273 ,  H03H17/028 ,  H03M3/30 ,  H03M3/37 ,  H03M3/47 ,  H04L25/02 ,  H04L27/02

Abstract: In one embodiment, a power amplification system of a radio-frequency transmitter includes a digital signal source that provides a digital input signal to an interleaved-bit-stream generator, which outputs a digital switching signal to a switching power amplifier. The interleaved-bit-stream generator has an eight-path interleaving architecture that helps reduce the effective clock-rate requirements of the interleaved-bit-stream generator. The interleaved-bit-stream generator includes an array of fractional-delay filters for receiving the digital input signal and outputting eight fractionally delayed digital output signals to a bit-stream generation array adapted to output eight corresponding bit streams to a serializer block that interleaves and combines the eight bit-streams into the digital switching signal. The relative phases of the interleaved signals may be adjusted to achieve certain desired effects.

公开(公告)号：US08824591B2

公开(公告)日：2014-09-02

申请号：US13660520

申请日：2012-10-25

Applicant: LSI Corporation

Inventor： Ross S. Wilson ,  Said E. Abdelli ,  Peter Kiss ,  Donald R. Laturell ,  James F. MacDonald

IPC: H04L27/00

CPC classification number: H04J3/0685

Abstract: A method and system for synchronous transfer of bitstream data between a power-driver chip and a digital signal processing chip in a digital radio frequency transmit system is disclosed. A master phase-locked-loop located in the power-driver chip is utilized to provide master clocking control for the digital radio frequency transmit system. Furthermore, the clocking method and system is configurable to secure precise carrier frequency positioning of a digitally-generated radio frequency signal based on predetermined chip frequencies unrelated to the carrier frequency, assuring low bitstream phase noise at the output of the power driver chip.

Abstract translation: 公开了一种用于在数字射频发射系统中的功率驱动器芯片和数字信号处理芯片之间同步传输比特流数据的方法和系统。 位于功率驱动器芯片中的主锁相环被用于为数字射频发射系统提供主时钟控制。 此外，时钟方法和系统可配置为基于与载波频率无关的预定码片频率来确保数字产生的射频信号的精确载波频率定位，确保在功率驱动器芯片的输出处的低位流相位噪声。

公开(公告)号：US20140168809A1

公开(公告)日：2014-06-19

申请号：US13719615

申请日：2012-12-19

Applicant: LSI CORPORATION

Inventor： Ross S. Wilson ,  Richard Rauschmayer

IPC: G11B20/10

CPC classification number: G11B20/10222

Abstract: An apparatus having a controller and a preamplifier is disclosed. The controller may be configured to generate information on a serial bus coupled to a preamplifier interface. The preamplifier may be configured to (i) generate a count value in response to a clock signal synchronized to a recording medium and (ii) generate a plurality of tag signals based on the information and the count value. The tag signals may gate a read operation and a write operation of the preamplifier.

Abstract translation: 公开了一种具有控制器和前置放大器的装置。 控制器可以被配置为在耦合到前置放大器接口的串行总线上产生信息。 前置放大器可以被配置为（i）响应于与记录介质同步的时钟信号产生计数值，以及（ii）基于该信息和计数值生成多个标签信号。 标签信号可以选通前置放大器的读取操作和写入操作。

公开(公告)号：US20140159991A1

公开(公告)日：2014-06-12

申请号：US13709743

申请日：2012-12-10

Applicant: LSI CORPORATION

Inventor： Peter Kiss ,  Said E. Abdelli ,  Kameran Azadet ,  Donald R. Laturell ,  James F. MacDonald ,  Ross S. Wilson

IPC: H03F1/00 ,  H03H11/00 ,  H01Q23/00

CPC classification number: H03H11/00 ,  H03F3/2175 ,  H03F3/24 ,  H03M3/50

Abstract: A switching power amplifier for multi-path signal interleaving includes a signal splitter configured to split a multi-bit source signal from a digital source into a plurality of multi-bit signals, one or more fractional delay filters configured to delay one or more signals of the plurality of signals by a selected time, a plurality of bit-stream converters, each bit-stream converter configured to receive one of the multi-bit signals, each bit-stream converter further configured to generate a single-bit signal based on a received multi-bit signal, a plurality of switching power amplifiers, each switching power amplifier configured to receive a single-bit signal from one of the bit-stream converters, and an interleaver configured to generate an interleaved output by interleaving two or more outputs of the switching power amplifiers, wherein a sampling frequency of the interleaved output of the interleaver is greater than the selected sampling frequency of the multi-bit source signal.

Abstract translation: 一种用于多径信号交织的开关功率放大器包括：信号分配器，被配置为将来自数字源的多位源信号分离成多个多位信号;一个或多个分数延迟滤波器，被配置为延迟一个或多个信号 所述多个信号经过选定的时间，多个比特流转换器，每个比特流转换器被配置为接收所述多比特信号中的一个，每个比特流转换器还被配置为基于所述多比特信号生成单比特信号 接收的多位信号，多个开关功率放大器，每个开关功率放大器被配置为从位流转换器之一接收单位信号;以及交织器，被配置为通过交织两个或多个输出 开关功率放大器，其中交织器的交错输出的采样频率大于所选择的多位源信号的采样频率。

公开(公告)号：US20140104716A1

公开(公告)日：2014-04-17

申请号：US13650474

申请日：2012-10-12

Applicant: LSI CORPORATION

Inventor： Ross S. Wilson ,  Jason S. Goldberg

IPC: G11B5/09

CPC classification number: G11B5/09

Abstract: An apparatus comprising a preamplifier, a channel, and a controller. The preamplifier may be configured to read/write data to a drive with a read/write head, in response to (i) a plurality of digital control signals multiplexed to be sent/received over a first bus and (ii) one or more analog data signals sent/received over a second bus. The channel may be configured to (i) connect to the first and second bus, and (ii) send/receive the plurality of digital control signals through (a) a plurality of interconnects and (b) the first bus. The controller may be configured to send/receive the digital control signals over the interconnects. The apparatus may be configured to (i) read/write the analog data signals to the drive and (ii) generate the digital control signals, in response to one or more input/output requests received from a drive interface.

Abstract translation: 一种包括前置放大器，通道和控制器的装置。 响应于（i）多路复用以通过第一总线发送/接收的多个数字控制信号，以及（ii）一个或多个模拟信号，前置放大器可以被配置为向具有读/写头的驱动器读/写数据 通过第二总线发送/接收的数据信号。 信道可以被配置为（i）连接到第一和第二总线，以及（ii）通过（a）多个互连和（b）第一总线发送/接收多个数字控制信号。 控制器可以被配置为通过互连发送/接收数字控制信号。 该装置可以被配置为（i）响应于从驱动器接口接收到的一个或多个输入/输出请求，将模拟数据信号读取/写入驱动器和（ii）生成数字控制信号。

公开(公告)号：US20140022876A1

公开(公告)日：2014-01-23

申请号：US14031701

申请日：2013-09-19

Applicant: LSI Corporation

Inventor： Ross S. Wilson

IPC: G11B13/04

CPC classification number: G11B13/04 ,  G11B5/02 ,  G11B20/10009 ,  G11B2005/0021

Abstract: Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

Abstract translation: 本发明的各种实施例提供了用于数据写入的系统和方法。 作为示例，讨论了包括读取电路，磁性写入电路，加热写入电路和环回电路的热辅助回路电路。 读取电路可操作以感测来自存储介质的数据，并将所感测的数据提供为读取输出。 磁写入电路可操作以提供与写入头的激励信号相对应的写入输出。 热写电路可操作以提供对应于热源的激励信号的热输出。 环回电路可操作以选择性地将热输出的导数耦合到读输出并选择性地将写输出的导数耦合到读输出。