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1.发明授权Method and apparatus for performing cache segment flush and cache segment invalidation operations 失效用于执行高速缓存段刷新和缓存段无效操作的方法和装置公开(公告)号：US06978357B1
公开(公告)日：2005-12-20
申请号：US09122349
申请日：1998-07-24
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804
摘要： A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.
摘要翻译： 一种用于在计算机系统中包括用于执行高速缓存存储器无效的指令和高速缓存存储器刷新操作的方法和装置。 在一个实施例中，计算机系统包括具有存储数据的多个高速缓存行和存储数据操作数的存储区域的高速缓冲存储器。 执行单元耦合到存储区域，并且响应于接收到单个指令，对数据操作数中的数据元素进行操作以使多个高速缓存行的预定部分中的数据无效。
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公开(公告)号：US6014735A
公开(公告)日：2000-01-11
申请号：US53391
申请日：1998-03-31
CPC分类号： G06F9/30185
摘要： The present invention discloses a method and apparatus for encoding an instruction in an instruction set which uses a prefix code to qualify an existing opcode of an existing instruction. An opcode and an escape code are selected. The escape code is selected such that it is different from the prefix code and the existing opcode. The opcode, the escape code, and the prefix code are combined to generate an instruction code which uniquely represents the operation performed by the instruction.
摘要翻译： 本发明公开了一种用于编码指令集中的指令的方法和装置，该指令使用前缀码来限定现有指令的现有操作码。 选择了操作码和转义码。 选择转义代码，使其与前缀代码和现有操作码不同。 操作码，转义码和前缀码被组合以产生唯一地表示指令执行的操作的指令代码。
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公开(公告)号：US06275904B1
公开(公告)日：2001-08-14
申请号：US09053385
申请日：1998-03-31
IPC分类号： G06F1208
CPC分类号： G06F12/0886 , G06F9/30018 , G06F9/30036 , G06F9/30047 , G06F12/0804 , G06F12/0888
摘要： A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
摘要翻译： 一种用于提供高速缓存存储器管理的计算机系统和方法。 计算机系统包括具有多个主存储器地址的主存储器，每个主存储器地址都具有对应的数据条目，以及耦合到主存储器的处理器。 至少一个高速缓存存储器耦合到处理器。 所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。 处理器接收具有操作数地址的指令，并确定操作数地址是否匹配高速缓存目录中的多个地址之一。 如果是这样，则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。 否则，更新与主存储器中的操作数地址相对应的数据条目。
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4.发明申请Method of treating, preventing, inhibiting or reducing damage to cardiac tissue with thymosin beta 4 fragments 审中-公开用胸腺素β4片段治疗，预防，抑制或减少心脏组织损伤的方法公开(公告)号：US20070191275A1
公开(公告)日：2007-08-16
申请号：US11649889
申请日：2007-01-05
申请人： Ewald Hannappel , Thomas Huff , Allan Goldstein
发明人： Ewald Hannappel , Thomas Huff , Allan Goldstein
IPC分类号： A61K38/17
CPC分类号： A61K38/07 , A61K38/2292
摘要： A method of treatment for promoting regeneration or repair a damaged cardiovascular tissue, or for preventing damage to cardiovascular tissue, includes administering to the tissue a damage-treating or -preventing fragment of thymosin beta 4 (Tβ4), such as AcSDKP, or a stimulating agent that forms such a fragment of (Tβ4).
摘要翻译： 用于促进再生或修复受损的心血管组织或用于预防对心血管组织的损伤的治疗方法包括向组织施用胸腺素β4（Tbeta4）的损伤治疗或预防性片段，例如AcSDKP，或刺激 形成（Tbeta4）片段的试剂。
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公开(公告)号：US06288723B1
公开(公告)日：2001-09-11
申请号：US09053259
申请日：1998-04-01
IPC分类号： G06T1500
CPC分类号： G06T15/005
摘要： An apparatus and method for performing conversion of graphical data format is disclosed. A matrix multiplication is performed on a first set of data and a second set of data to generate a third set of data in a first format. The first and second sets of data represent the graphical data. The third set of data in the first format is transmitted to a graphics card. The third set of data in the first format is converted to a converted set of data in a second format.
摘要翻译： 公开了一种用于执行图形数据格式的转换的装置和方法。 对第一组数据和第二组数据执行矩阵乘法以生成第一格式的第三组数据。 第一和第二组数据表示图形数据。 第一格式的第三组数据被传送到图形卡。 第一格式的第三组数据被转换为第二格式的转换的数据集。
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公开(公告)号：US20080248993A1
公开(公告)日：2008-10-09
申请号：US11722979
申请日：2006-01-17
IPC分类号： A61K38/02
CPC分类号： C07K14/57581 , A61K38/00
摘要： A composition including an oxidized or superoxidized methionine-containing beta thymosin peptide, isoform thereof, fragment thereof, isolated R-enantiomer thereof or isolated S-enantiomer thereof, other than racemic thymosin beta 4 sulfoxide, or a modified beta thymosin peptide, isoform or fragment thereof with an amino acid substituent substituted for at least one methionine of an amino acid sequence of a normally methionine-containing beta thymosin peptide, isoform or fragment thereof, and method for forming same.
摘要翻译： 包含氧化或超氧化的含甲硫氨酸的β胸腺素肽，其同种型，其片段，其分离的R-对映异构体或其分离的S-对映异构体，除外消旋胸腺素β4亚砜，或经修饰的β胸腺素肽，同种型或片段 的氨基酸取代基取代至少一种含有正常甲硫氨酸的β-胸腺素肽，同种型或其片段的氨基酸序列的甲硫氨酸及其形成方法。
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公开(公告)号：US06898700B2
公开(公告)日：2005-05-24
申请号：US09053398
申请日：1998-03-31
申请人： William C. Alexander, III , Shreekant S. Thakkar , Patrice L. Roussel , Thomas Huff , Bryant E. Bigbee , Stephen A. Fischer
发明人： William C. Alexander, III , Shreekant S. Thakkar , Patrice L. Roussel , Thomas Huff , Bryant E. Bigbee , Stephen A. Fischer
CPC分类号： G06F9/30043 , G06F9/462
摘要： The present invention discloses a method and apparatus for saving and restoring registers. A single instruction is decoded. The single instruction moves contents of a plurality of registers associated with a functional unit in a processor to a memory; the processor operates under a plurality of operational modes and operand sizes. The single instruction arranges the contents in the memory according to a predetermined format into a plurality of groups, each group is aligned at an address boundary which corresponds to a multiple of 2N bytes. The predetermined format is constant for the plurality of operational modes and operand sizes. The single instruction retains the contents of the plurality of registers after moving.
摘要翻译： 本发明公开了一种保存和恢复寄存器的方法和装置。 单个指令被解码。 单个指令将与处理器中的功能单元相关联的多个寄存器的内容移动到存储器; 处理器在多种操作模式和操作数大小下工作。 单个指令根据预定格式将内容排列到多个组中，每组在对应于2×N个字节的倍数的地址边界对齐。 对于多个操作模式和操作数大小，预定格式是恒定的。 单指令在移动后保留多个寄存器的内容。
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公开(公告)号：US20060100156A1
公开(公告)日：2006-05-11
申请号：US11240636
申请日：2005-10-03
申请人： Ewald Hannappel , Thomas Huff , Allan Goldstein , David Crockford
发明人： Ewald Hannappel , Thomas Huff , Allan Goldstein , David Crockford
CPC分类号： C07K7/06 , A61K38/00 , C07K2319/09
摘要： A pharmaceutically acceptable composition and method for entering a cell nucleus utilizes a cell nucleus-entering polypeptide including at least one of amino acid sequence LKKTET, amino acid sequence LKKTNT or amino acid sequence KSKLKK, or a conservative variant thereof, linked to a physiologically active agent having at least one of therapeutic or diagnostic application in the cell nucleus.
摘要翻译： 用于进入细胞核的药学上可接受的组合物和方法利用细胞核进入多肽，其包括与生理活性剂连接的氨基酸序列LKKTET，氨基酸序列LKKTNT或氨基酸序列KSKLKK或其保守变体中的至少一种 具有在细胞核中的治疗或诊断应用中的至少一种。
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公开(公告)号：US06211892B1
公开(公告)日：2001-04-03
申请号：US09053389
申请日：1998-03-31
申请人： Thomas Huff , Shreekant S. Thakkar
发明人： Thomas Huff , Shreekant S. Thakkar
IPC分类号： G06T1522
CPC分类号： G06T15/005
摘要： An apparatus and method for performing an intra-add operation on packed data using computer-implemented steps is described. A processor is coupled to a hardware unit which transmits data representing graphics to another computer or display. A storage device coupled to the processor, has stored therein a routine, which, when executed by the processor, causes the processor to generate the data. The routine causes the processor to at least access a first packed data operand having at least one pair of data elements; swap positions of the data elements within the at least one pair of data elements to generate a second packed data operand, add data elements starting at the same bit positions from the first and second packed data operands to generate a third packed data operand.
摘要翻译： 描述了使用计算机实现的步骤对打包数据执行加入内操作的装置和方法。 处理器耦合到将表示图形的数据传送到另一计算机或显示器的硬件单元。 耦合到处理器的存储设备，其中存储有例程，当由处理器执行时，处理器产生数据。 该例程使处理器至少访问具有至少一对数据元素的第一打包数据操作数; 在所述至少一对数据元素内的所述数据元素的交换位置以产生第二打包数据操作数，从所述第一和第二打包数据操作数添加从相同位位置开始的数据元素，以生成第三打包数据操作数。
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公开(公告)号：US6115812A
公开(公告)日：2000-09-05
申请号：US53308
申请日：1998-04-01
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036
摘要： An apparatus and method for performing vertical parallel operations on packed data is described. A first set of data operands and a second set of data operands are accessed. Each of these sets of data represents graphical data stored in a first format. The first set of data operands is convereted into a converted set and the second set of data operands is replicated to generate a replicated set. A vertical matrix multiplication is performed on the converted set and the replicated set to generate transformed graphical data.
摘要翻译： 描述了用于对打包数据执行垂直并行操作的装置和方法。 访问第一组数据操作数和第二组数据操作数。 这些数据集中的每一组表示以第一格式存储的图形数据。 第一组数据操作数被转换成转换的集合，并且第二组数据操作数被复制以生成复制集合。 对转换的集合和复制集执行垂直矩阵乘法以生成转换的图形数据。
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