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22 条记录 (耗时 0.024 秒)

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    3.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US07250669B2

    公开(公告)日：2007-07-31

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L29/00

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    4.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US06869884B2

    公开(公告)日：2005-03-22

    申请号：US10225828

    申请日：2002-08-22

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Method of fabricating circular or angular spiral MIM capacitors
    8.
    发明申请
    Method of fabricating circular or angular spiral MIM capacitors 审中-公开
    制造圆形或角螺旋MIM电容器的方法

    公开(公告)号：US20050086780A1

    公开(公告)日：2005-04-28

    申请号：US10692029

    申请日：2003-10-23

    申请人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

    发明人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

    IPC分类号： H01L27/08 ,  H01G7/00 ,  H01K3/10

    CPC分类号： H01L27/0805 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49165

    摘要： A method of forming a capacitor comprising the following steps. A substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

    摘要翻译： 一种形成电容器的方法，包括以下步骤。 具有形成在其上的下部低k电介质层的衬底设置有介电常数小于约3.0的下部低k电介质层。 金属垂直电极板形成在下部低k电介质层内，使得相邻的金属垂直电极板之间具有较低的低k电介质层部分。 在相邻的金属垂直电极板之间的较低的低k电介质层部分被具有大于约3.0的介电常数的高k电介质材料沟槽部分代替。

    Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process
    9.
    发明申请
    Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process 有权
    用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管

    公开(公告)号：US20070134854A1

    公开(公告)日：2007-06-14

    申请号：US11302479

    申请日：2005-12-13

    申请人： Shaoqiang Zhang ,  Purakh Verma ,  Sanford Chu

    发明人： Shaoqiang Zhang ,  Purakh Verma ,  Sanford Chu

    IPC分类号： H01L21/8232 ,  H01L21/335

    CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

    摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

    摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。

    Method of forming an inductor with continuous metal deposition
    10.
    发明申请
    Method of forming an inductor with continuous metal deposition 审中-公开
    形成具有连续金属沉积的电感器的方法

    公开(公告)号：US20050124131A1

    公开(公告)日：2005-06-09

    申请号：US11034932

    申请日：2005-01-13

    申请人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    发明人： Chit Hweing ,  Lap Chan ,  Purakh Verma ,  Yelehanka Ramachandramurthy Pradeep ,  Sanford Chu

    IPC分类号： H01F17/00 ,  H01L21/02 ,  H01L23/522 ,  H01L21/20 ,  H01L29/00

    CPC分类号： H01L28/10 ,  H01F17/0006 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is described to fabricate RF inductor devices on a silicon substrate. Low-k or other dielectric material is deposited and patterned to form inductor lower plate trenches. Trenches are lined with barrier film such as TaN, filled with copper, and excess metal planarized using chemical mechanical polishing (CMP). Second layer of a dielectric material is deposited and patterned to form via-hole/trenches. Via-hole/trench patterns are filled with barrier material, and the dielectric film in between the via-hole/trenches is etched to form a second set of trenches. These trenches are filled with copper and planarized. A third layer of a dielectric film is deposited and patterned to form via-hole/trenches. Via-hole/trenches are then filled with barrier material, and the dielectric film between via-hole/trench patterns etched to form a third set of trenches. These trenches are filled with copper metal and excess metal removed by CMP to form said RF inductor.

    摘要翻译： 描述了在硅衬底上制造RF电感器件的方法。 沉积低k或其他电介质材料并图案化以形成电感器下板沟槽。 沟槽衬有阻挡膜，如填充有铜的TaN和使用化学机械抛光（CMP）平坦化的多余金属。 介电材料的第二层被沉积并图案化以形成通孔/沟槽。 通孔/沟槽图案填充有阻挡材料，蚀刻通孔/沟槽之间的电介质膜以形成第二组沟槽。 这些沟槽用铜填充并平坦化。 电介质膜的第三层被沉积并图案化以形成通孔/沟槽。 然后用阻挡材料填充通孔/沟槽，蚀刻通孔/沟槽图案之间的电介质膜以形成第三组沟槽。 这些沟槽填充有铜金属，并通过CMP去除多余的金属以形成所述RF电感器。