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公开(公告)号：US4912476A
公开(公告)日：1990-03-27
申请号：US730119
申请日：1985-05-03
IPC分类号： G05B19/414 , H01Q3/00
CPC分类号： H01Q3/005 , G05B19/4142 , G05B2219/31137 , G05B2219/33254 , G05B2219/34219 , G05B2219/45001
摘要： An improved interface arrangement between an antenna controller and one or more antennas. The interface includes a reduced number of control lines but is capable of handling complete interface requirements including control and status between the antenna controller and the antenna.
摘要翻译： 天线控制器与一个或多个天线之间的改进的接口布置。 该接口包括减少数量的控制线，但是能够处理完整的接口要求，包括天线控制器和天线之间的控制和状态。
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公开(公告)号：US4680759A
公开(公告)日：1987-07-14
申请号：US660742
申请日：1984-10-15
CPC分类号： H04J3/1682
摘要： A multiplexer system which operates as a standard multiplexer as well as a proportional multiplexer by providing typical multiplexing operation by one circuit portion and proportional multiplexing operation by other portions of the circuit wherein the multiplexer system can interface with a plurality of users or user devices in such a way that data streams between the user devices and the multiplexer system can be reallocated so as to enhance data transfer irrespective of the clock-to-data relationship such that no data is lost during circuit operation. The proportional MUX can be selectively controlled by a microprocessor.
摘要翻译： 一种多路复用器系统，其通过提供一个电路部分的典型多路复用操作以及电路其他部分的比例多路复用操作，作为标准多路复用器和比例复用器工作，其中多路复用器系统可以与多个用户或用户设备接口 可以重新分配用户设备和多路复用器系统之间的数据流的方式，以便与时钟到数据关系无关地增强数据传输，使得在电路操作期间没有数据丢失。 比例MUX可以由微处理器选择性地控制。
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公开(公告)号：US4685106A
公开(公告)日：1987-08-04
申请号：US646015
申请日：1984-08-31
CPC分类号： H04J3/062 , H04J3/1647
摘要： A high rate multiplexing system which is capable of operating on multiple channels while ensuring synchronization of the system operation. The system includes a basic timing network for synchronizing the system operation. Automatic phase adjusters are used to re-align data signals with a clock signal whenever data transitions occur while the data is being sampled. Synchronizing circuits are used to insert synchronization data bits into the multiplexed data streams where appropriate. A medium rate multiplexer generates two different data streams, certain clock signals and strobe signals. A higher rate multiplexer is capable of operation in different modes, including but not limited to wideband operation or narrow band operation. A Manchester encoder combines data output signals into a single aggregate data stream.
摘要翻译： 一种能够在确保系统操作同步的同时在多个通道上运行的高速率复用系统。 该系统包括用于同步系统操作的基本定时网络。 当数据被采样时，当数据转换发生时，自动相位调整器用于将数据信号与时钟信号重新对准。 使用同步电路将适当的同步数据位插入多路复用数据流。 中速率复用器产生两个不同的数据流，某些时钟信号和选通信号。 较高速率的多路复用器能够以不同的模式操作，包括但不限于宽带操作或窄带操作。 曼彻斯特编码器将数据输出信号组合成单个聚合数据流。
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公开(公告)号：US4771426A
公开(公告)日：1988-09-13
申请号：US886771
申请日：1986-07-17
摘要： An electronic system for providing a stable, isochronous clock signal with very low jitter and slew rate to thereby permit multiplexing of data from an external source which is not synchronous with the multiplexer frame rate.
摘要翻译： 一种电子系统，用于提供具有非常低的抖动和转换速率的稳定的同步时钟信号，从而允许来自与多路复用器帧速率不同步的外部源的数据的多路复用。
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公开(公告)号：US4394642A
公开(公告)日：1983-07-19
申请号：US304434
申请日：1981-09-21
CPC分类号： G06F7/76 , H03M13/271 , H03M13/2785
摘要： A novel interleaver-de-interleaver is provided which is adapted to store bits of a data stream after being error encoded. The data bits are stored in a random access memory in addresses identifiable by an array of columns and rows. The interleaver comprises address pointer means and logic for reading the data bits out of the memory addresses in a predetermined reordered sequence to provide a quasi-random pattern sequence of data bits which when transmitted are substantially immune to periodic bursts of radio frequency interference signals.
摘要翻译： 提供了一种新颖的交错器去交错器，其适于在错误编码之后存储数据流的位。 数据位存储在随机访问存储器中，地址可由列和行数组标识。 交织器包括地址指针装置和用于以预定的重排序列从存储器地址中读出数据位的逻辑，以提供数据比特的准随机模式序列，当被发送时基本上不受周期性的射频干扰信号的突发的影响。
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公开(公告)号：US4573155A
公开(公告)日：1986-02-25
申请号：US561502
申请日：1983-12-14
CPC分类号： H03M13/39
摘要： A novel maximum likelihood sequence detector is provided for decoding linear cyclic error correction codes. The detector comprises one cyclic correlator for each two shaft sets of the code which have weights greater than one, and a serial correlator for detecting the shift sets of all zero's and all one's. The number of cyclic correlators required to decode linear codes is reduced to less than half the number of shift sets which define all the codewords instead of half the number of codewords where the number of shift sets is always less than the number of codewords.
摘要翻译： 提供了一种用于解码线性循环纠错码的新型最大似然序列检测器。 检测器包括一个循环相关器，用于每个具有权重大于1的代码的两组轴组，以及串行相关器，用于检测全零和全部的移位组。 将线性码解码所需的循环相关器的数量减少到少于移位组的数目的一半，这些移位组限定了所有的码字，而不是码字数量的一半，其中移位组的数量总是小于码字数。
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7.发明授权System and method for clocking data between a remote unit and a local unit 失效用于在远程单元和本地单元之间对数据进行计时的系统和方法
公开(公告)号：US4208724A
公开(公告)日：1980-06-17
申请号：US842639
申请日：1977-10-17
申请人： Glen D. Rattlingourd
发明人： Glen D. Rattlingourd
CPC分类号： H04L7/0338 , H04L25/05 , H04L7/0008
摘要： An automatic clock phase adjustment circuit is incorporated in a local unit of a data clocking system. The local unit also includes a clock pulse generator and a local data storage device. The system also includes a remote unit having a remote data storage device. The automatic clock phase adjustment circuit receives clock pulses from the generator and produces output clock pulses having first and second half periods interconnected by a clocking transition which when applied to the remote storage device causes clocking out of data to the local storage device. The circuit also produces a sampling pulse during each of the first and second half periods of the output clock pulses and is operable to detect in which particular one of the half periods a positive transition in the incoming data has occurred during the interval of a sampling pulse in that half period. This permits the circuit to produce local or input clock pulses for clocking in the incoming data at the local storage device during the other of the half periods so that the clocking edges of the input clock pulses will not coincide with any of the positive transitions of the incoming data when applied to the local storage device. As a result, reliable storage of the incoming data is guaranteed to occur at the local storage device at times when the data is stable.
摘要翻译： 自动时钟相位调整电路被并入数据时钟系统的本地单元中。 本地单元还包括时钟脉冲发生器和本地数据存储设备。 该系统还包括具有远程数据存储设备的远程单元。 自动时钟相位调整电路从发生器接收时钟脉冲，并产生具有通过时钟转换互连的第一和第二半周期的输出时钟脉冲，当时钟转换被应用于远程存储装置时，使得数据向本地存储装置输出。 电路还在输出时钟脉冲的第一和第二半周期的每一个期间产生采样脉冲，并且可操作以在采样脉冲的间隔期间检测在半个周期中哪个特定的一个周期内进入数据中的正跳变已经发生 在那个半个时期。 这允许电路产生本地或输入时钟脉冲，用于在半个周期中的另一个期间在本地存储设备处输入数据的时钟脉冲，使得输入时钟脉冲的时钟边缘将不与任何正向跃迁 应用于本地存储设备时的传入数据。 因此，当数据稳定时，保证输入数据的可靠存储在本地存储设备处发生。
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公开(公告)号：US4164022A
公开(公告)日：1979-08-07
申请号：US903278
申请日：1978-05-05
CPC分类号： G06F17/10 , G06F1/03 , G06F2101/04
摘要： Electronic digital apparatus for computing an approximation of the arctangent of a given tangent number, N, being in the range of 0 to 1 and in binary form, operates in two stages to provide a solution of the expression: ##EQU1## During the first stage, steps are taken by the apparatus to find out where within the range of 0 to 1, divided preferably into four equal increments, the known tangent number N is located. When the correct increment represented by one of a plurality of increment numbers I.sub.j stored in a ROM unit of the apparatus is found, then one of a like plurality of center numbers C.sub.k of that increment also stored in the ROM unit may be readily selected, as can also be the corresponding one of a plurality of stored numbers A.sub.i representing the arctangents of the stored center numbers C.sub.k. During the first stage, the product number C.sub.k (N) is also formed. In the second stage of operation of the apparatus, the dividend and divisor numbers N-C.sub.k and 1+C.sub.k (N) are first calculated. The quotient number,(N-C.sub.k)/[1+C.sub.k (N)],is then calculated. Finally, the Arctan (C.sub.k), such being the selected one of the arctangent numbers A.sub.i, is accessed from the ROM unit and added to the quotient which gives, as an approximation, the value of the unknown angle.
摘要翻译： 用于计算给定正切数N的反正切近似值的电子数字装置N在0至1和二进制形式的范围内，分两个阶段进行操作以提供以下表达式的解：<第一阶段 该装置采取步骤来找出在0到1的范围内的哪里，优选地分成四个相等的增量，已知的切线数N位于。 当存储在设备的ROM单元中的多个增量号Ij中的一个表示的正确增量被找到时，也可以容易地选择该存储在ROM单元中的增量的类似多个中心号Ck中的一个，如 也可以是表示存储的中心号码Ck的反正切的多个存储号码Ai中的对应的一个。 在第一阶段，也形成产品编号Ck（N）。 在设备的第二操作阶段，首先计算除数和除数N-Ck和1 + Ck（N）。 然后计算商数（N-Ck）/ [1 + Ck（N）]。 最后，Arctan（Ck）是从ROM单元访问的所选择的反正切数量Ai之一，并将其加到给出作为近似值的未知角度值的商。
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公开(公告)号：US5257282A
公开(公告)日：1993-10-26
申请号：US625497
申请日：1984-06-28
CPC分类号： H04L9/0662 , H04L2209/125
摘要： A novel low speed code sequence generator having a set of parallel flip-flops is provided and comprises a vector generator in series between the outputs and the inputs of the set of parallel flip-flops in the generator. The outputs from the low speed code sequence generator may be multiplexed together to provide an individual high speed code sequence. The selective outputs from a plurality of low speed code sequence generators may be algebraically combined and then multiplexed together to provide a composite code sequence.
摘要翻译： 提供了一种具有一组并行触发器的新颖的低速码序列发生器，其包括串联在输出端和发生器中并联触发器组的输入端之间的矢量发生器。 来自低速码序列发生器的输出可以被复用在一起以提供单独的高速码序列。 来自多个低速码序列发生器的选择性输出可以被代数组合，然后被多路复用在一起以提供复合码序列。
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公开(公告)号：US4791390A
公开(公告)日：1988-12-13
申请号：US394488
申请日：1982-07-01
CPC分类号： H03H21/0012
摘要： A very rapidly converging adaptive filter which uses a variable scale factor for each weight of the filter. The value of the variable scale factor is chosen for each iteration and is based upon the sign changes of the incremental weight change. The variable scale factor exhibits large values when no sign changes occur and smaller values when sign changes occur. The new filter provides considerable improvement in increase of convergence rate and decrease in residual errors even in the presence of heavy noise while requiring only a modest increase in hardware.
摘要翻译： 一个非常快速收敛的自适应滤波器，其对滤波器的每个权重使用可变比例因子。 为每次迭代选择可变比例因子的值，并基于增量权重变化的符号变化。 当发生符号变化时，可变比例因子表现出较大的值，当发生符号变化时，变量比例因子显示较小的值。 新的滤波器在收敛速度的增加和残留误差的降低方面都有很大的改进，即使在存在高噪声的同时也只需要适度的硬件增加。
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