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    MPEG video decoder having a high bandwidth memory
    1.
    发明授权
    MPEG video decoder having a high bandwidth memory 失效
    具有高带宽存储器的MPEG视频解码器

    公开(公告)号：US5623311A

    公开(公告)日：1997-04-22

    申请号：US330579

    申请日：1994-10-28

    申请人： Larry Phillips ,  Shuji Inoue ,  Edwin R. Meyer

    发明人： Larry Phillips ,  Shuji Inoue ,  Edwin R. Meyer

    IPC分类号： H04N11/04 ,  G06T9/00 ,  G09G5/39 ,  H03M7/36 ,  H04N5/44 ,  H04N7/015 ,  H04N7/26 ,  H04N7/30 ,  H04N7/32 ,  H04N7/50 ,  H04N7/56 ,  H04N7/12

    CPC分类号： H04N7/56 ,  H04N19/174 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N7/015 ,  G09G2360/123 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91 ,  H04N5/4401

    摘要： A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value. The count value is compared to a succession of externally supplied system clock reference (SCR) values to generate a phase difference signal that is used to adjust the frequency of the signal produced by the DPLL. In addition, the DPLL is aligned in phase by substituting respective portions of the SCR value for the count value developed by the DPLL and for the accumulated phase value used by the DPLL.

    摘要翻译： 根据MPEG-2标准编码的视频信号的解码器包括单个高带宽存储器和数字锁相环。 该内存具有单个内存端口。 存储器用于保持1）输入比特流，2）用于运动补偿处理的第一和第二参考帧，以及3）表示当前正在解码的字段的图像数据。 解码器包括存储和取出比特流数据的电路，获取参考帧数据，以块格式存储当前正被解码的字段的图像数据，并且获取该图像数据以转换为光栅扫描格式。 所有这些存储器访问操作都是时分复用的，并使用单个存储器端口。 数字锁相环（DPLL）计算在MPEG-2标准中定义的27MHz系统时钟信号的脉冲，以产生计数值。 将计数值与一系列外部提供的系统时钟参考（SCR）值相比较，以产生用于调整DPLL产生的信号频率的相位差信号。 此外，DPLL通过将SCR值的各部分替换为由DPLL产生的计数值和DPLL使用的累加相位值来对齐。

    HDTV raster converter and interpolation filter with section overlap
    2.
    发明授权
    HDTV raster converter and interpolation filter with section overlap 失效
    HDTV光栅转换器和具有部分重叠的插值滤波器

    公开(公告)号：US5485215A

    公开(公告)日：1996-01-16

    申请号：US246308

    申请日：1994-05-19

    申请人： Edwin R. Meyer ,  Saiprasad V. Naimpally ,  Larry Phillips ,  Shuji Inoue

    发明人： Edwin R. Meyer ,  Saiprasad V. Naimpally ,  Larry Phillips ,  Shuji Inoue

    IPC分类号： H04N7/01 ,  H04N7/015 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12

    CPC分类号： H04N7/015 ,  H04N19/436 ,  H04N19/61 ,  H04N19/85 ,  H04N7/01 ,  H04N7/0125 ,  H04N19/30

    摘要： A system and method for filtering a digital signal having a relatively high data rate uses circuitry which operates at a lower data rate. The filter includes an input section which receives the input signal and which divides the input signal into a plurality of contiguous segments. The system also includes a first filter which receives samples representing one of the plurality of segments and adjacent samples from the next contiguous one of the segments and which filters all of the received samples to produce a first filtered signal. A second filter receives samples of the next contiguous segment and filters those samples to produce a second filtered signal. The filtered signals are combined by providing the samples of the second filtered signal immediately after the samples of the first filtered signal to produce a filtered output signal. The invention also relates to using respective timing signals associated with the segments to determine when the samples of the first and second filtered signals are provided.

    摘要翻译： 用于对具有相对较高数据速率的数字信号进行滤波的系统和方法使用以较低数据速率操作的电路。 滤波器包括输入部分，其接收输入信号并且将输入信号划分成多个连续的段。 该系统还包括第一滤波器，其接收表示来自下一个相邻片段之一的多个片段和相邻样本中的一个的样本，并且对所接收的所有样本进行滤波以产生第一滤波信号。 第二滤波器接收下一连续段的采样并对这些采样进行滤波以产生第二滤波信号。 通过在第一滤波信号的采样之后立即提供第二滤波信号的样本来组合经滤波的信号，以产生经滤波的输出信号。 本发明还涉及使用与这些段相关联的相应定时信号来确定何时提供第一和第二滤波信号的采样。

    DISPLAY DEVICE, EYEGLASS DEVICE AND IMAGE SYSTEM
    5.
    发明申请
    DISPLAY DEVICE, EYEGLASS DEVICE AND IMAGE SYSTEM 有权
    显示装置，眼镜装置和图像系统

    公开(公告)号：US20120154371A1

    公开(公告)日：2012-06-21

    申请号：US13398138

    申请日：2012-02-16

    申请人： Kazuhiro MIHARA ,  Hiroshi Mitani ,  Shuji Inoue ,  Masanobu Inoe ,  Katsuo Saigo ,  Seiji Nakazawa

    发明人： Kazuhiro MIHARA ,  Hiroshi Mitani ,  Shuji Inoue ,  Masanobu Inoe ,  Katsuo Saigo ,  Seiji Nakazawa

    IPC分类号： G09G5/00

    CPC分类号： G08C19/16 ,  H04N13/341

    摘要： A display device including: a display portion for displaying a video; a generator for generating a synchronization signal including a command signal synchronized with display of frame images of the video; and a transmitter for transmitting the synchronization signal, wherein the command signal including a predetermined member of pulse signals has a leading pulse signal for notifying a start of the command signal, a terminal pulse signal for notifying an end of the command signal, and a control pulse signal for notifying a content of synchronization control synchronized with the display of the frame images.

    摘要翻译： 一种显示装置，包括：用于显示视频的显示部分; 发生器，用于产生包括与所述视频的帧图像的显示同步的命令信号的同步信号; 以及发送器，用于发送同步信号，其中包括脉冲信号的预定成员的命令信号具有用于通知命令信号开始的前导脉冲信号，用于通知命令信号结束的终端脉冲信号和控制 脉冲信号，用于通知与帧图像的显示同步的同步控制的内容。

    Method for determining motion compensation
    6.
    再颁专利
    Method for determining motion compensation 有权

    公开(公告)号：USRE39281E1

    公开(公告)日：2006-09-12

    申请号：US10895283

    申请日：2004-07-21

    申请人： Takeshi Yukitake ,  Shuji Inoue

    发明人： Takeshi Yukitake ,  Shuji Inoue

    IPC分类号： H04N7/12

    摘要： A method for predicting motion compensation for determining of an input image based on a motion vector of the input image from this input image to a reference image which has been sampled at a first set time, and the method includes calculating a motion vector of the input image based on a move, at a second set time, of a block unit which is a part of the input image and consists of a plurality of pixels, and calculating a motion vector of the reference image based on a move, at the first set time, of a block unit which is a part of the reference image and consists of a plurality of pixels. Move compensation of the input image is calculated both from the motion vector of the input image and from the motion vector of the reference image, to thereby realize a method for determining motion compensation with high precision.

    Method for determining motion compensation
    7.
    再颁专利
    Method for determining motion compensation 有权

    公开(公告)号：USRE39280E1

    公开(公告)日：2006-09-12

    申请号：US09866811

    申请日：2001-05-30

    申请人： Takeshi Yukitake ,  Shuji Inoue

    发明人： Takeshi Yukitake ,  Shuji Inoue

    IPC分类号： H04N7/32

    摘要： A method for predicting motion compensation for determining of an input image based on a motion vector of the input image from this input image to a reference image which has been sampled at a first set time, and the method includes calculating a motion vector of the input image based on a move, at a second set time, of a block unit which is a part of the input image and consists of a plurality of pixels, and calculating a motion vector of the reference image based on a move, at the first set time, of a block unit which is a part of the reference image and consists of a plurality of pixels. Move compensation of the input image is calculated both from the motion vector of the input image and from the motion vector of the reference image, to thereby realize a method for determining motion compensation with high precision.

    Dynamic resource management for distributed retrieval system for security
    8.
    发明申请
    Dynamic resource management for distributed retrieval system for security 有权
    用于安全性的分布式检索系统的动态资源管理

    公开(公告)号：US20050066331A1

    公开(公告)日：2005-03-24

    申请号：US10665772

    申请日：2003-09-19

    申请人： Shuji Inoue ,  Kuo Lee ,  Hasan Ozdemir

    发明人： Shuji Inoue ,  Kuo Lee ,  Hasan Ozdemir

    IPC分类号： G06F9/00 ,  G06F9/50 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L29/08

    CPC分类号： G06F9/505 ,  G06F9/5044 ,  G06F2209/5021 ,  G06F2209/508 ,  G08B13/19656 ,  G08B13/19673 ,  H04L67/1002 ,  H04L67/1008 ,  H04L67/101

    摘要： A resource manager allocates operation requests to security network devices according to device characteristics. The devices collect and/or manage data from an environment. The devices may include a camera, a multimedia recorder, an analyzer, and a meta-data server. One or more users submit operation requests to a controller. The controller allocates the network devices to the operation requests according to the device characteristics. The device characteristics include availability of the device, media flow data of the device, location of the device, and capabilities of the device.

    摘要翻译： 资源管理器根据设备特性向安全网络设备分配操作请求。 设备收集和/或管理环境中的数据。 设备可以包括相机，多媒体记录器，分析器和元数据服务器。 一个或多个用户向控制器提交操作请求。 控制器根据设备特性将网络设备分配给操作请求。 设备特征包括设备的可用性，设备的媒体流数据，设备的位置以及设备的能力。

    Variable length code look-up table having separate code length determination
    10.
    发明授权
    Variable length code look-up table having separate code length determination 失效
    具有单独代码长度确定的可变长度代码查找表

    公开(公告)号：US5550542A

    公开(公告)日：1996-08-27

    申请号：US238362

    申请日：1994-05-04

    申请人： Shuji Inoue

    发明人： Shuji Inoue

    IPC分类号： H04N7/26 ,  H03M7/42 ,  H04N1/41 ,  H03M7/40

    CPC分类号： H03M7/425

    摘要： A variable length decoder for decoding a variable length code. The variable length decoder includes a code length look-up table which receives n-j bits of an n-bit fixed-length word. A segment of the variable length code value is held in the n-j bits where n and j are integers and j is less than or equal to n. The code length look-up table produces a decoded code length value. The variable length decoder includes a code value look-up table which receives the n-bit fixed-length word and produces a decoded code value of the variable length code.

    摘要翻译： 一种用于解码可变长度码的可变长度解码器。 可变长度解码器包括接收n位固定长度字的n-j个比特的码长查找表。 可变长度代码值的段被保存在n-j位中，其中n和j是整数，并且j小于或等于n。 码长查找表产生解码码长度值。 可变长度解码器包括接收n位固定长度字并产生可变长度码的解码码值的码值查找表。