公开(公告)号：US5418617A

公开(公告)日：1995-05-23

申请号：US742398

申请日：1991-08-08

申请人： Saiprasad V. Naimpally ,  Siu-Leong Iu ,  Edwin R. Meyer

发明人： Saiprasad V. Naimpally ,  Siu-Leong Iu ,  Edwin R. Meyer

IPC分类号： H04N7/32 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12

CPC分类号： H04N19/567 ,  H04N19/51 ,  H04N19/61

摘要： Apparatus for selecting a block of data in a previous frame to be used as a predicted block for a given block in a current frame in a system that reduces the bit rate by codifying the difference between the predicted block and the given block in a given manner by deriving the differences between the given block in the current frame and a plurality of blocks in the previous frame and selecting as the predicted block that block for which the codification of its differences with the given block requires the least number of bits. The apparatus can also select a predicted block from a number of blocks selected in accordance with ABD or SBD techniques.

摘要翻译： 用于选择要用作系统中当前帧中的给定块的预测块的先前帧中的数据块的装置，其通过以给定方式编码预测块和给定块之间的差异来降低比特率 通过导出当前帧中的给定块与前一帧中的多个块之间的差异，并选择作为其与给定块的差异的编码所需的最少位数的块的预测块。 该装置还可以从根据ABD或SBD技术选择的多个块中选择预测块。

公开(公告)号：US5623311A

公开(公告)日：1997-04-22

申请号：US330579

申请日：1994-10-28

申请人： Larry Phillips ,  Shuji Inoue ,  Edwin R. Meyer

发明人： Larry Phillips ,  Shuji Inoue ,  Edwin R. Meyer

IPC分类号： H04N11/04 ,  G06T9/00 ,  G09G5/39 ,  H03M7/36 ,  H04N5/44 ,  H04N7/015 ,  H04N7/26 ,  H04N7/30 ,  H04N7/32 ,  H04N7/50 ,  H04N7/56 ,  H04N7/12

CPC分类号： H04N7/56 ,  H04N19/174 ,  H04N19/42 ,  H04N19/423 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61 ,  H04N7/015 ,  G09G2360/123 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91 ,  H04N5/4401

摘要： A decoder for a video signal encoded according to the MPEG-2 standard includes a single high-bandwidth memory and a digital phase-locked loop. This memory has a single memory port. The memory is used to hold 1) the input bit-stream, 2) first and second reference frames used for motion compensated processing, and 3) image data representing a field that is currently being decoded. The decoder includes circuitry which stores and fetches the bit-stream data, fetches the reference frame data, stores the image data for the field that is currently being decoded in block format and fetches this image data for conversion to raster-scan format. All of these memory access operations are time division multiplexed and use the single memory port. The digital phase locked loop (DPLL) counts pulses of a 27 MHz system clock signal, defined in the MPEG-2 standard, to generate a count value. The count value is compared to a succession of externally supplied system clock reference (SCR) values to generate a phase difference signal that is used to adjust the frequency of the signal produced by the DPLL. In addition, the DPLL is aligned in phase by substituting respective portions of the SCR value for the count value developed by the DPLL and for the accumulated phase value used by the DPLL.

摘要翻译： 根据MPEG-2标准编码的视频信号的解码器包括单个高带宽存储器和数字锁相环。 该内存具有单个内存端口。 存储器用于保持1）输入比特流，2）用于运动补偿处理的第一和第二参考帧，以及3）表示当前正在解码的字段的图像数据。 解码器包括存储和取出比特流数据的电路，获取参考帧数据，以块格式存储当前正被解码的字段的图像数据，并且获取该图像数据以转换为光栅扫描格式。 所有这些存储器访问操作都是时分复用的，并使用单个存储器端口。 数字锁相环（DPLL）计算在MPEG-2标准中定义的27MHz系统时钟信号的脉冲，以产生计数值。 将计数值与一系列外部提供的系统时钟参考（SCR）值相比较，以产生用于调整DPLL产生的信号频率的相位差信号。 此外，DPLL通过将SCR值的各部分替换为由DPLL产生的计数值和DPLL使用的累加相位值来对齐。

公开(公告)号：US5541595A

公开(公告)日：1996-07-30

申请号：US246115

申请日：1994-05-19

申请人： Edwin R. Meyer

发明人： Edwin R. Meyer

IPC分类号： H03M7/42 ,  H03M7/40

CPC分类号： H03M7/425

摘要： A variable length decoder for decoding a variable length code. The variable length decoder includes a first look-up table for receiving and decoding the most significant bits of the variable length code and for producing a first decoded code corresponding to the most significant bits. The first look-up table means also for outputs a conversion signal. In addition, a second look-up table is provided for receiving and decoding the least significant bits and for producing a second decoded code corresponding to the least significant bits. The first look-up table and the second look-up table decode the most significant bits and the least significant bits at substantially the same time. The decoded output of the look-up tables is provided to a selector. The selector selects the first decoded code or the second decoded code based upon the conversion signal.

摘要翻译： 一种用于解码可变长度码的可变长度解码器。 可变长度解码器包括用于接收和解码可变长度码的最高有效位并且用于产生对应于最高有效位的第一解码码的第一查找表。 第一查询表也用于输出转换信号。 此外，提供第二查找表用于接收和解码最低有效位并产生对应于最低有效位的第二解码码。 第一查找表和第二查找表在基本相同的时间解码最高有效位和最低有效位。 将查找表的解码输出提供给选择器。 选择器基于转换信号选择第一解码码或第二解码码。

公开(公告)号：US5053862A

公开(公告)日：1991-10-01

申请号：US339032

申请日：1989-04-14

申请人： Larry G. Phillips ,  Edwin R. Meyer ,  David C. Greene

发明人： Larry G. Phillips ,  Edwin R. Meyer ,  David C. Greene

IPC分类号： H04N5/073 ,  H04N5/265 ,  H04N5/45 ,  H04N9/44

CPC分类号： H04N9/44

摘要： A method and apparatus for synchronizing a received television signal to a subcarrier locked signal is provided. The apparatus includes a comparison block for determining whether the received television signal and subcarrier locked signal are related by a predetermined fixed frequency relationship and for providing indications of the same, and a signal generation block for dividing down the subcarrier locked signal according to the predetermined fixed frequency relationship so as to provide an output signal which is synchronized with the subcarrier locked signal, and at a frequency determined according to the fixed frequency relationship when the signals are related. The apparatus is particularly useful in PIP applications where the received television signal is a horizontal signal and the subcarrier locked signal is a four times multiple of the subcarrier frequency. The comparison block preferably includes a counter and a windowing circuit for determining whether edges of horizontal signal pulses are received within or outside a predetermined time window, and a decision circuit for determining whether the occurrences (counts) of in and out of window edges are indicative of related or unrelated signals. The entire apparatus preferably includes only flip-flops, simple logic gates such as AND, NAND, or OR gates, inverters, multiplexer switches, and resettable counters. The apparatus also preferably further includes a standard combination of flip-flops and a NAND gate for providing a synchronized horizontal reset output signal when the comparison block determines that the received horizontal clock and the subcarrier locked clock are not related.

公开(公告)号：US5534944A

公开(公告)日：1996-07-09

申请号：US505581

申请日：1995-07-21

申请人： Ren Egawa ,  Edwin R. Meyer

发明人： Ren Egawa ,  Edwin R. Meyer

IPC分类号： H04N7/26 ,  G06T9/00 ,  G11B27/036 ,  H03M7/30 ,  H04N5/38 ,  H04N5/92 ,  H04N7/08 ,  H04N7/081 ,  H04N7/24 ,  H04N7/32 ,  H04N7/50 ,  H04N9/74

CPC分类号： H04N21/23424 ,  G06T9/007 ,  G11B27/036 ,  H04N19/132 ,  H04N19/142 ,  H04N19/152 ,  H04N19/162 ,  H04N19/172 ,  H04N19/186 ,  H04N19/61 ,  H04N21/23406 ,  H04N21/23611 ,  H04N19/146 ,  H04N19/50

摘要： A method of splicing two compressed video signals which have been encoded according to the standard adopted by the Moving Picture Experts Group (MPEG) determines an amount of null information that is to be inserted between the two video signals in order to ensure that an input buffer of an MPEG decoder does not overflow after receiving the spliced video signals. The method allows a splice to occur after any access unit (picture) in the first compressed video signal. The amount of null information is determined from the data rates of the first and second compressed video signals and the amount of new data which is provided to the buffer before the data is retrieved from the buffer for both the first and second video signals. The video signals are spliced by inserting the null information, as sequence stuffing bits into a buffer immediately after the selected picture in the first video signal. The second video signal is transmitted to the buffer immediately after these stuffing bits.

摘要翻译： 已经根据运动图像专家组（MPEG）采用的标准编码的两个压缩视频信号的拼接方法确定要在两个视频信号之间插入的空信息量，以确保输入缓冲器 MPEG解码器在接收到拼接视频信号之后不会溢出。 该方法允许在第一压缩视频信号中的任何访问单元（图片）之后发生拼接。 从第一和第二压缩视频信号的数据速率以及在缓冲器中为第一和第二视频信号检索数据之前提供给缓冲器的新数据量确定空信息量。 通过在第一视频信号中的所选择的图像之后立即将空信息作为序列填充比特插入到缓冲器中来将视频信号进行拼接。 在这些填充位之后立即将第二视频信号发送到缓冲器。

公开(公告)号：US5485215A

公开(公告)日：1996-01-16

申请号：US246308

申请日：1994-05-19

申请人： Edwin R. Meyer ,  Saiprasad V. Naimpally ,  Larry Phillips ,  Shuji Inoue

发明人： Edwin R. Meyer ,  Saiprasad V. Naimpally ,  Larry Phillips ,  Shuji Inoue

IPC分类号： H04N7/01 ,  H04N7/015 ,  H04N7/26 ,  H04N7/50 ,  H04N7/12

CPC分类号： H04N7/015 ,  H04N19/436 ,  H04N19/61 ,  H04N19/85 ,  H04N7/01 ,  H04N7/0125 ,  H04N19/30

摘要： A system and method for filtering a digital signal having a relatively high data rate uses circuitry which operates at a lower data rate. The filter includes an input section which receives the input signal and which divides the input signal into a plurality of contiguous segments. The system also includes a first filter which receives samples representing one of the plurality of segments and adjacent samples from the next contiguous one of the segments and which filters all of the received samples to produce a first filtered signal. A second filter receives samples of the next contiguous segment and filters those samples to produce a second filtered signal. The filtered signals are combined by providing the samples of the second filtered signal immediately after the samples of the first filtered signal to produce a filtered output signal. The invention also relates to using respective timing signals associated with the segments to determine when the samples of the first and second filtered signals are provided.

摘要翻译： 用于对具有相对较高数据速率的数字信号进行滤波的系统和方法使用以较低数据速率操作的电路。 滤波器包括输入部分，其接收输入信号并且将输入信号划分成多个连续的段。 该系统还包括第一滤波器，其接收表示来自下一个相邻片段之一的多个片段和相邻样本中的一个的样本，并且对所接收的所有样本进行滤波以产生第一滤波信号。 第二滤波器接收下一连续段的采样并对这些采样进行滤波以产生第二滤波信号。 通过在第一滤波信号的采样之后立即提供第二滤波信号的样本来组合经滤波的信号，以产生经滤波的输出信号。 本发明还涉及使用与这些段相关联的相应定时信号来确定何时提供第一和第二滤波信号的采样。

公开(公告)号：US5008740A

公开(公告)日：1991-04-16

申请号：US339044

申请日：1989-04-14

申请人： Larry G. Phillips ,  Edwin R. Meyer ,  David C. Greene

发明人： Larry G. Phillips ,  Edwin R. Meyer ,  David C. Greene

IPC分类号： H04N9/64

CPC分类号： H04N9/64

摘要： Apparatus and methods for remodulating digital luminance and color difference components for display as PIP information, or together with other composite video components for multi-PIP and test pattern applications are disclosed. A digital encoder is used for conducting a digital quadrature modulation on the color difference components and for digitally adding the luminance signal thereto prior to the converting of the remodulated information into an analog format. Preferably, the digital video information output by the encoder is in the form Y1+(R-Y)1, Y1 +(B-Y)1, Y2-(R-Y)1, Y2-(B-Y)1, Y3+(R-Y)2. Y3+(b-Y)2, Y4 -(R-Y)2, . . . , where Y is the luminance component, R-Y and B-Y are color difference components, and where the numbers index received samples of the video components with the luminance component being sampled at twice the frequency of the color difference components. Where digitally modulated composite video is desired, fixed black level, burst, and background values are multiplexed with the active R-Y and B-Y signals, while fixed sync tip, black level, and background values are multiplexed with the active Y signals prior to encoding.

摘要翻译： 公开了用于重新调制用于显示为PIP信息的数字亮度和色差分量的装置和方法，或与用于多PIP和测试图案应用的其他复合视频组件一起。 数字编码器用于对色差分量进行数字正交调制，并在将重新调制的信息转换为模拟格式之前，对其亮度信号进行数字加法。 优选地，由编码器输出的数字视频信息为Y1 +（R-Y）1，Y1 +（B-Y）1，Y2-（R-Y）1，Y2-（B-Y）1，Y3 +（R-Y） Y3 +（b-Y）2，Y4 - （R-Y）2， 。 。 其中Y是亮度分量，R-Y和B-Y是色差分量，并且其中以亮度分量被采样的视频分量的接收采样的数目为两倍于色差分量的频率。 在需要数字调制复合视频的情况下，固定黑电平，脉冲串和背景值与有源R-Y和B-Y信号多路复用，而固定同步提示，黑电平和背景值在编码之前与有效Y信号进行复用。

公开(公告)号：US4809069A

公开(公告)日：1989-02-28

申请号：US166279

申请日：1988-03-10

申请人： Edwin R. Meyer ,  Saiprasad V. Naimpally

发明人： Edwin R. Meyer ,  Saiprasad V. Naimpally

IPC分类号： H04N5/262 ,  H04N5/21 ,  H04N5/44 ,  H04N5/45 ,  H04N9/64 ,  H04N5/208 ,  H04N5/272

CPC分类号： H04N5/4448 ,  H04N5/21 ,  H04N5/45 ,  H04N7/012 ,  H04N9/646

摘要： A digital television processing section capable of picture enhancement, progressive scanning, and multiple picture-in-picture processing is provided. The preferred digital television processing section preferably comprises a picture enhancement processor (PEP), a progressive scan processor, a picture in picture processor, at least one multiplexing means, and a common memory means. The PEP broadly comprises a parameter control means, a memory input select means, and mixer for obtaining current video data, delayed video data from the common memory, and control information from the control means, and for processing the obtained data and information to provide a signal to the progressive scan processor. In various modes of operation, the mixer also provides the signal to the memory input select means which forwards the information to the common memory. The common memory is used as a field delay device and feeds a delayed signal forward to the progressive scan processor. The progressive scan processor then utilizes the current signal and the delayed signal to provide a non-interlaced display. The delayed signal from the common memory may also be fed back to the mixer of the PEP so that noise reduction and/or cross-color effect reduction may be accomplished or so that stored pictures may be displayed. The picture-in-picture (PIP) processor together with a first multiplexer permits main and secondary (PIP) video data to be supplied as current video data to the PEP. Or if desired, up to nine PIPs may constitute the video field.

公开(公告)号：US20100079679A1

公开(公告)日：2010-04-01

申请号：US12570497

申请日：2009-09-30

申请人： Antin U. KULCZYCKYJ ,  Edwin R. Meyer ,  Daniel E. Mocelo ,  Larry G. Phillips

发明人： Antin U. KULCZYCKYJ ,  Edwin R. Meyer ,  Daniel E. Mocelo ,  Larry G. Phillips

IPC分类号： H04N5/63

CPC分类号： H04N5/63 ,  H04N5/4401 ,  H04N7/106 ,  H04N21/4181 ,  H04N21/4182 ,  H04N21/4436 ,  H04N21/6118

摘要： An integrated cable-ready digital TV receiver includes a digital TV receiver system, a cable receiver system, a power control system for controlling a first power supply to the digital TV receiver system and a second power supply to the cable receiver system. The power control system is configured to control the first and second power supply according to a condition including a first condition and a second condition of the integrated cable-ready digital TV. In the first condition, the power control system supplies the first power to the digital TV receiver system but does not provide the second power to the cable receiver system. In the second condition, the power control system supplies the first power to the digital TV receiver system and the second power to the cable receiver system.

摘要翻译： 一种集成的有线就绪数字电视接收机包括数字电视接收机系统，电缆接收机系统，用于控制数字TV接收机系统的第一电源的电力控制系统和电缆接收机系统的第二电源。 功率控制系统被配置为根据包括集成电缆就绪数字TV的第一状态和第二状态的条件来控制第一和第二电源。 在第一种情况下，功率控制系统将第一功率提供给数字TV接收机系统，但不向电缆接收机系统提供第二功率。 在第二种情况下，功率控制系统将第一功率提供给数字TV接收机系统，并将第二功率提供给电缆接收机系统。

公开(公告)号：US5502493A

公开(公告)日：1996-03-26

申请号：US246272

申请日：1994-05-19

申请人： Edwin R. Meyer

发明人： Edwin R. Meyer

IPC分类号： G06T9/00 ,  H03M7/42 ,  H04N7/26 ,  H04N7/30 ,  H04N7/12

CPC分类号： H03M7/425 ,  H04N19/60 ,  H04N19/13 ,  H04N19/91

摘要： The present invention is embodied in a decoder for a video signal encoded according to the standard proposed by the Moving Pictures Expert Group (MPEG) of the International Standards Organization (ISO). This decoder employs four sets of processors, each set containing three processors that operate concurrently to decode the MPEG-2 video signal. A variable length decoder processes the input stream to decode the variable length encoded data. The operations performed by this decoding processor change depending on the type of data being decoded. These changes are implemented using a master Digital Signal Processor (DSP) which is programmed according to the MPEG-2 syntax. The data decoded by the VLD processor is either video data or control data. The control data is divided into two types, control data needed to reproduce the image and control data that describes the bit-stream. The control data needed to decode the image is passed to a control DSP while the control data which describes the bit-stream is passed to the master DSP. To ensure that the entire system can operate with sufficient speed to decode an image in real time, this group of three processors is duplicated four times in the system. Each set of processors operates in parallel and handles digital data representing a distinct portion of the final high definition television image.

摘要翻译： 本发明体现在根据由国际标准组织（ISO）的运动图像专家组（MPEG）提出的标准编码的视频信号的解码器中。 该解码器采用四组处理器，每组包含三个同时操作的处理器，以对MPEG-2视频信号进行解码。 可变长度解码器处理输入流以对可变长度编码数据进行解码。 由该解码处理器执行的操作根据正被解码的数据的类型而改变。 这些更改使用根据MPEG-2语法编程的主数字信号处理器（DSP）来实现。 由VLD处理器解码的数据是视频数据或控制数据。 控制数据被分为两种类型，即再现图像所需的控制数据和描述比特流的控制数据。 将图像解码所需的控制数据传递给控制DSP，同时将描述比特流的控制数据传递给主DSP。 为了确保整个系统能够以足够的速度运行以实时解码图像，该组三个处理器在系统中重复四次。 每组处理器并行操作，处理表示最终高分辨率电视图像的不同部分的数字数据。