公开(公告)号：US5912571A

公开(公告)日：1999-06-15

申请号：US947776

申请日：1997-10-09

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： G11C5/14 ,  G11C8/08 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/22 ,  G11C5/143 ,  G11C8/08 ,  H03K17/223

摘要： A semiconductor device disables itself during power-up until the internal power supply voltage and other circuits reach states in which the device can operate properly. The internal power supply voltage is coupled to the input terminal of an inverter through a delay network. During power-up, the device remains disabled until the voltage at the input terminal of the inverter reaches the inverter trip point. The delay network and the inverter are designed so that the voltage at the inverter's input terminal does not reach the inverter trip point until the internal power supply voltage and other circuits have reached states in which the device can operate properly. When the (device is turned off, the inverter input terminal is discharged quickly by a diode or resistor. Therefore, if the power is turned back on immediately, a suitable delay will be provided.

摘要翻译： 一个半导体器件在上电时会自动关闭，直到内部电源电压和其他电路达到设备可以正常工作的状态。 内部电源电压通过延迟网络耦合到逆变器的输入端。 在上电期间，器件保持禁止，直到变频器输入端的电压到达变频器跳闸点。 延时网络和逆变器的设计使得在内部电源电压和其他电路达到设备正常工作的状态之前，变频器输入端子的电压不会到达变频器跳闸点。 当设备关闭时，变频器输入端子被二极管或电阻器快速放电，因此如果电源立即返回，则会提供适当的延时。

公开(公告)号：US5757710A

公开(公告)日：1998-05-26

申请号：US760124

申请日：1996-12-03

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

公开(公告)号：US5844296A

公开(公告)日：1998-12-01

申请号：US717471

申请日：1996-09-20

申请人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

发明人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

IPC分类号： H01L21/8242 ,  H01L23/525 ,  H01L23/58 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5258 ,  H01L27/10894 ,  H01L2924/0002

摘要： A compact laser programmable fuse structure has a central line and two sets of fuses extending from opposite sides of the central line. An opening through a passivation layer exposes the fuses and overlies the central line. In one embodiment, the opening also exposes the portions of the central line. The central line is made of fuse material or another material for which the opening does not create reliability problems. In one embodiment of the invention, the central line and the fuses are parts of a single contiguous region of polysilicon. This fuse structure has a length that is about half the length of conventional fuse structure having the same number of fuses because two fuses, one on either side of the central line, fit within a length used for a single fuse in conventional fuse structures.

摘要翻译： 紧凑的激光可编程熔丝结构具有中心线和两组从中心线的相对侧延伸的保险丝。 通过钝化层的开口露出熔丝并覆盖中心线。 在一个实施例中，开口也暴露中心线的部分。 中心线由保险丝材料或其他材料制成，开口不会产生可靠性问题。 在本发明的一个实施例中，中心线和熔丝是多晶硅的单个连续区域的部分。 这种熔丝结构的长度大约是具有相同数量的保险丝的常规熔断器结构的长度的一半，因为两个保险丝（一个位于中心线的任一侧上）都配合在常规保险丝结构中用于单个保险丝的长度内。

公开(公告)号：US5838072A

公开(公告)日：1998-11-17

申请号：US805391

申请日：1997-02-24

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： H01L23/50 ,  H01L23/52 ,  H01L23/28 ,  H01L23/48

CPC分类号： H01L24/49 ,  H01L23/50 ,  H01L23/52 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/14

摘要： An integrated circuit has a supply node for supplying power to at least one intermediate node coupled to circuitry for receiving power. Rather than transmit power from the supply node to the intermediate node by means of a power bus formed as part of the chip interconnect structure, power is supplied to an external wire which is coupled from the supply to the intermediate node. Other than as connected to the supply node and intermediate node, the wire is electrically isolated from the die. This structure and method for making the semiconductor package allow power to be distributed within a semiconductor chip without sacrificing valuable chip space and without requiring a special lead frame for distributing the power within the semiconductor chip.

摘要翻译： 集成电路具有用于向耦合到用于接收功率的电路的至少一个中间节点供电的供电节点。 不是通过形成为芯片互连结构的一部分的电源总线将功率从供电节点传输到中间节点，而是将电力供应到从电源耦合到中间节点的外部电线。 除了连接到供电节点和中间节点之外，导线与模具电隔离。 用于制造半导体封装的这种结构和方法允许电力分配在半导体芯片内，而不牺牲有价值的芯片空间，而不需要用于在半导体芯片内分配功率的特殊引线框架。

公开(公告)号：US6011737A

公开(公告)日：2000-01-04

申请号：US967436

申请日：1997-11-11

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/00

CPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

摘要翻译： 交错的位线读出放大器架构利用电路来模拟未选择用于连接到激活的存储器单元的每个边沿读出放大器上的存储器单元的影响，从而允许边缘读出放大器与内部的读出放大器同时激活 到存储器阵列，没有烧毁边缘读出放大器的危险。 该结构消除了通常与交错的共享位线读出放大器架构中使用的边缘读出放大器相关联的地址解码电路，从而降低了这种存储器阵列的复杂性并减小了其尺寸。

公开(公告)号：US5838622A

公开(公告)日：1998-11-17

申请号：US850933

申请日：1997-02-28

申请人： Lawrence C. Liu ,  Li-Chun Li ,  Michael A. Murray

发明人： Lawrence C. Liu ,  Li-Chun Li ,  Michael A. Murray

IPC分类号： G11C8/06 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C8/06 ,  G11C11/4082

摘要： A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

摘要翻译： 长X位或长Y位存储在锁存器中，并用于补充非对称DRAM存储器中的Y地址位，从而允许一部分用于需要长X位的设计，并且还用于需要 长Y位

公开(公告)号：US5781488A

公开(公告)日：1998-07-14

申请号：US844541

申请日：1997-04-18

申请人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

发明人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/1051

摘要： In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

摘要翻译： 根据本发明，具有交错位线读出放大器配置的DRAM利用I / O数据路径方案，其使通过I / O数据路径的时间延迟最小化。 DRAM包括第一和第二存储器阵列，其中第一外部读出放大器经由第一列解码电路在输入端子上接收对应于从第一存储器阵列选择的存储器单元的状态的信号。 第二外部读出放大器经由第二列解码电路在输入端子上接收对应于从第二存储器阵列选择的存储器单元的状态的信号。 两个外部读出放大器中的每一个具有一起短接的输出端子。 使用两个外部读出放大器中的每一个的另一个输入端子的三态信号来消除短路输出端子上的数据争用。

公开(公告)号：US5966338A

公开(公告)日：1999-10-12

申请号：US47304

申请日：1998-03-24

申请人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

发明人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/1051

摘要： In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

摘要翻译： 根据本发明，具有交错位线读出放大器配置的DRAM利用I / O数据路径方案，其使通过I / O数据路径的时间延迟最小化。 DRAM包括第一和第二存储器阵列，其中第一外部读出放大器经由第一列解码电路在输入端子上接收对应于从第一存储器阵列选择的存储器单元的状态的信号。 第二外部读出放大器经由第二列解码电路在输入端子上接收对应于从第二存储器阵列选择的存储器单元的状态的信号。 两个外部读出放大器中的每一个具有一起短接的输出端子。 使用两个外部读出放大器中的每一个的另一个输入端子的三态信号来消除短路输出端子上的数据争用。

公开(公告)号：US5828609A

公开(公告)日：1998-10-27

申请号：US760125

申请日：1996-12-03

申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/00

CPC分类号： G11C11/4099 ,  G11C11/4091 ,  G11C7/065

摘要： The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.

摘要翻译： 在感测放大器的导通期间，动态随机存取存储器中的高电压轨上的电压被控制，以通过连接芯片外部的电压源将其保持在集成电路芯片内部的电压源的大致电压 直到电源轨上的电压等于芯片内部电压源的电压，此时外部电压源断开。

公开(公告)号：US5761112A

公开(公告)日：1998-06-02

申请号：US717031

申请日：1996-09-20

申请人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

发明人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/24

CPC分类号： G11C7/1048 ,  G11C7/065

摘要： A DRAM has a sensing circuit which includes an on-chip capacitors having a total capacitance greater than about 35% of the total capacitance of the bit lines. The on-chip capacitors are coupled to a power line of the sense amplifiers and stabilizes a power supply voltage to prevent voltage drop and noise during the large sensing currents for a read/refresh cycle. A read/refresh cycle in accordance with an embodiment of the invention includes precharging bit lines and the on-chip capacitors before connecting memory transistors to the bit lines and connecting power to the sense amplifiers. Capacitors can be formed in any available space in the integrated circuit particularly in space under metal bus lines in peripheral circuitry surrounding a memory array.

摘要翻译： DRAM具有感测电路，该感测电路包括具有大于位线的总电容的约35％的总电容的片上电容器。 片上电容器耦合到读出放大器的电源线，并稳定电源电压，以防止在读/刷新周期的大感应电流期间的电压降和噪声。 根据本发明的实施例的读取/刷新周期包括在将存储器晶体管连接到位线之前预充电位线和片上电容器，并将功率连接到读出放大器。 电容器可以在集成电路的任何可用空间中形成，特别是在围绕存储器阵列的外围电路中的金属总线下方的空间中。