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    DEVICES FOR REDUCTION OF POST OPERATIVE ILEUS
    4.
    发明申请
    DEVICES FOR REDUCTION OF POST OPERATIVE ILEUS 审中-公开
    用于减少手术后的装置

    公开(公告)号：US20080086078A1

    公开(公告)日：2008-04-10

    申请号：US11856773

    申请日：2007-09-18

    申请人： Darrel M. Powell ,  Mark Pomeroy ,  Michael A. Murray ,  Carl J. Shurtleff

    发明人： Darrel M. Powell ,  Mark Pomeroy ,  Michael A. Murray ,  Carl J. Shurtleff

    IPC分类号： A61M31/00 ,  A61B17/11 ,  A61B17/115

    CPC分类号： A61B17/072 ,  A61B17/07292 ,  A61B17/115 ,  A61B2017/00893

    摘要： An apparatus and method for reducing post-operative ileus and/or gastric stasis is described. The method can include applying to the intestine a therapeutically effective amount of a composition comprising a drug that is effective in reducing post-operative ileus and/or gastric stasis, such as by introducing the composition through a surgical access device, such as a trocar or endoscope. The apparatus can include a surgical fastener and a buttress comprising the composition.

    摘要翻译： 描述了用于减少术后肠梗阻和/或胃潴留的装置和方法。 该方法可以包括将治疗有效量的包含有效减少手术后肠梗阻和/或胃潴留的药物的组合物施用于肠道，例如通过将组合物通过外科进入装置如套针针或 内窥镜 该装置可以包括外科紧固件和包括该组合物的支撑件。

    Dram with new I/O data path configuration
    6.
    发明授权
    Dram with new I/O data path configuration 失效
    引入新的I / O数据路径配置

    公开(公告)号：US5966338A

    公开(公告)日：1999-10-12

    申请号：US47304

    申请日：1998-03-24

    申请人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

    发明人： Lawrence C. Liu ,  Michael A. Murray ,  Li-Chun Li

    IPC分类号： G11C7/10 ,  G11C11/4096 ,  G11C7/02

    CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/1051

    摘要： In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

    摘要翻译： 根据本发明，具有交错位线读出放大器配置的DRAM利用I / O数据路径方案，其使通过I / O数据路径的时间延迟最小化。 DRAM包括第一和第二存储器阵列，其中第一外部读出放大器经由第一列解码电路在输入端子上接收对应于从第一存储器阵列选择的存储器单元的状态的信号。 第二外部读出放大器经由第二列解码电路在输入端子上接收对应于从第二存储器阵列选择的存储器单元的状态的信号。 两个外部读出放大器中的每一个具有一起短接的输出端子。 使用两个外部读出放大器中的每一个的另一个输入端子的三态信号来消除短路输出端子上的数据争用。

    Generation of signals from other signals that take time to develop on power-up
    7.
    发明授权
    Generation of signals from other signals that take time to develop on power-up 失效
    生成来自其他信号的信号，在上电时需要时间进行开发

    公开(公告)号：US5907257A

    公开(公告)日：1999-05-25

    申请号：US853291

    申请日：1997-05-09

    申请人： Lawrence Liu ,  Michael A. Murray ,  Li-Chun Li

    发明人： Lawrence Liu ,  Michael A. Murray ,  Li-Chun Li

    IPC分类号： G05F1/46 ,  G05F1/10

    CPC分类号： G05F1/468 ,  G05F1/465

    摘要： A bias voltage generator generates the same bias voltage VBB for different external power supply voltages EVCC (for example, for EVCC=3.3V or 5.0V). During power-up, the charge pump that generates VBB is controlled by an enable signal ExtEn referenced to EVCC. Later an internal supply voltage IVCC becomes fully developed to a value independent from EVCC (for example, IVCC=3.0V), and the charge pump becomes controlled by an enable signal IntEn referenced to IVCC. This enable signal IntEn will cause VBB to reach its target value, for example, -1.5V. This target value is independent of EVCC. During power-up, when the charge pump is controlled by ExtEn, the bias voltage VBB is driven to an intermediate value (for example, -0.5V or -1V). This intermediate value depends on EVCC, but is below the target value in magnitude. The intermediate value reduces the likelihood of latch-up during power-up, but the intermediate value does not go beyond the target value thus does not create a significant pn-junction current leakage in semiconductor regions to which the bias voltage is applied.

    摘要翻译： 偏置电压发生器为不同的外部电源电压EVCC产生相同的偏置电压VBB（例如，对于EVCC = 3.3V或5.0V）。 在上电期间，产生VBB的电荷泵由参考EVCC的使能信号ExtEn控制。 之后，内部电源电压IVCC完全发展为独立于EVCC（例如，IVCC = 3.0V）的值，并且电荷泵由参考IVCC的使能信号IntEn控制。 该启用信号IntEn将使VBB达到其目标值，例如-1.5V。 该目标值与EVCC无关。 在上电期间，当电荷泵由ExtEn控制时，偏置电压VBB被驱动到中间值（例如，-0.5V或-1V）。 该中间值取决于EVCC，但是在大小上低于目标值。 中间值降低了在上电期间闭锁的可能性，但是中间值不超过目标值，因此在施加偏置电压的半导体区域中不会产生显着的pn结电流泄漏。

    Sterile occlusion fasteners and instrument and method for their placement
    8.
    发明授权
    Sterile occlusion fasteners and instrument and method for their placement 失效
    无菌咬合紧固件及其放置方法

    公开(公告)号：US5833700A

    公开(公告)日：1998-11-10

    申请号：US741803

    申请日：1996-10-31

    申请人： Mark Fogelberg ,  J. David Hughett ,  C. Kerwin Braddock ,  Michael E. Boehm ,  David Stefanchik ,  Michael A. Murray

    发明人： Mark Fogelberg ,  J. David Hughett ,  C. Kerwin Braddock ,  Michael E. Boehm ,  David Stefanchik ,  Michael A. Murray

    IPC分类号： A61B17/122 ,  A61B17/128 ,  A61B17/00

    CPC分类号： A61B17/1227 ,  A61B17/122 ,  A61B17/1285 ,  Y10S227/902

    摘要： A clip, clip applier and method for ligating a tissue structure is provided. The applier has a two stage actuation. In the first stage, a tissue structure is positioned into the jaws of the clip applier The jaws close and lock to a preset force to compress and temporarily occlude the tissue structure. If satisfactorily positioned, the second stage is initiated in which a clip is advanced through the shaft of the clip applier in a closed position. At the distal end of the clip applier, the clip is opened slightly to capture the pre-compressed tissue structure, and is placed over the structure. The clip is then dissociated from the business end of the instrument. Preferably the clip comprises two leg members disposed in close proximity to one another joined from opposing directions by a connecting element. The connecting element restricts separation of the leg members with opposing spring members so as to provide substantially uniform parallel deflection of the leg members from each other.

    摘要翻译： 提供了一种用于结扎组织结构的夹子，夹持器和方法。 施肥机具有两级致动。 在第一阶段中，组织结构被定位在夹具的夹爪中。夹爪闭合并锁定到预设的力以压缩并暂时闭塞组织结构。 如果令人满意地定位，则启动第二阶段，其中夹子在关闭位置通过夹具施加器的轴推进。 在施放器的远端处，夹子稍微打开以捕获预压缩的组织结构，并且被放置在结构上。 然后将剪辑从仪器的业务端解离。 优选地，夹子包括通过连接元件彼此紧密相邻地布置成由相反方向连接的两个腿部构件。 连接元件限制腿构件与相对的弹簧构件的分离，以便使腿构件彼此基本均匀地平行地偏转。

    Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking
    9.
    发明授权
    Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking 失效
    模拟DRAM存储器位线/位线用于电路定时和电压电平跟踪

    公开(公告)号：US5828609A

    公开(公告)日：1998-10-27

    申请号：US760125

    申请日：1996-12-03

    申请人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

    发明人： Li-Chun Li ,  Lawrence C. Liu ,  Michael A. Murray

    IPC分类号： G11C7/06 ,  G11C11/4091 ,  G11C11/4099 ,  G11C7/00

    CPC分类号： G11C11/4099 ,  G11C11/4091 ,  G11C7/065

    摘要： The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.

    摘要翻译： 在感测放大器的导通期间，动态随机存取存储器中的高电压轨上的电压被控制，以通过连接芯片外部的电压源将其保持在集成电路芯片内部的电压源的大致电压 直到电源轨上的电压等于芯片内部电压源的电压，此时外部电压源断开。

    Charge storage for sensing operations in a DRAM
    10.
    发明授权
    Charge storage for sensing operations in a DRAM 失效
    充电存储用于DRAM中的感测操作

    公开(公告)号：US5761112A

    公开(公告)日：1998-06-02

    申请号：US717031

    申请日：1996-09-20

    申请人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

    发明人： Michael A. Murray ,  Lawrence C. Liu ,  Li-Chun Li

    IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/24

    CPC分类号： G11C7/1048 ,  G11C7/065

    摘要： A DRAM has a sensing circuit which includes an on-chip capacitors having a total capacitance greater than about 35% of the total capacitance of the bit lines. The on-chip capacitors are coupled to a power line of the sense amplifiers and stabilizes a power supply voltage to prevent voltage drop and noise during the large sensing currents for a read/refresh cycle. A read/refresh cycle in accordance with an embodiment of the invention includes precharging bit lines and the on-chip capacitors before connecting memory transistors to the bit lines and connecting power to the sense amplifiers. Capacitors can be formed in any available space in the integrated circuit particularly in space under metal bus lines in peripheral circuitry surrounding a memory array.

    摘要翻译： DRAM具有感测电路，该感测电路包括具有大于位线的总电容的约35％的总电容的片上电容器。 片上电容器耦合到读出放大器的电源线，并稳定电源电压，以防止在读/刷新周期的大感应电流期间的电压降和噪声。 根据本发明的实施例的读取/刷新周期包括在将存储器晶体管连接到位线之前预充电位线和片上电容器，并将功率连接到读出放大器。 电容器可以在集成电路的任何可用空间中形成，特别是在围绕存储器阵列的外围电路中的金属总线下方的空间中。