公开(公告)号：US6081603A

公开(公告)日：2000-06-27

申请号：US925022

申请日：1997-09-08

申请人： Lawrence D. Engh ,  Jung Sheng Hoei ,  Vishal Sarin

发明人： Lawrence D. Engh ,  Jung Sheng Hoei ,  Vishal Sarin

IPC分类号： H03G3/12 ,  H03G1/00 ,  H03G3/30 ,  H03F21/00

CPC分类号： H03G3/3005 ,  H03G1/007

摘要： The present invention relates to a method and apparatus for adjusting the gain of an amplifier circuit. A gain control circuit compares the output of the amplifier with a reference voltage and adjusts a variable resistor, thereby altering the gain of the amplifier.

摘要翻译： 本发明涉及一种用于调整放大器电路的增益的方法和装置。 增益控制电路将放大器的输出与参考电压进行比较，并调整可变电阻，从而改变放大器的增益。

公开(公告)号：US5859803A

公开(公告)日：1999-01-12

申请号：US925020

申请日：1997-09-08

申请人： Hagop Nazarian ,  David Sowards ,  Lawrence D. Engh ,  Jung Sheng Hoei ,  May Lee

发明人： Hagop Nazarian ,  David Sowards ,  Lawrence D. Engh ,  Jung Sheng Hoei ,  May Lee

IPC分类号： G11C29/52 ,  G11C7/00 ,  H01L21/00

CPC分类号： G11C29/52

摘要： The present invention discloses a circuit for controlling operation of a functional circuit in a device based on a test result during testing. The circuit comprises a first storage element configured to be in one of a first state and a second state according to the test result, and a first sensing element coupled to the first storage element for generating a first signal used to control the operation of the functional circuit.

摘要翻译： 本发明公开了一种电路，用于根据测试中的测试结果控制设备中的功能电路的操作。 电路包括根据测试结果被配置为处于第一状态和第二状态之一的第一存储元件，以及耦合到第一存储元件的第一感测元件，用于产生用于控制功能的操作的第一信号 电路。

公开(公告)号：US6035049A

公开(公告)日：2000-03-07

申请号：US924215

申请日：1997-09-05

申请人： Lawrence D. Engh ,  Jung Sheng Hoei ,  Vashal Sarin

发明人： Lawrence D. Engh ,  Jung Sheng Hoei ,  Vashal Sarin

IPC分类号： H03F3/00 ,  H03H19/00 ,  H03F21/00

CPC分类号： H03H19/004 ,  H03F3/005

摘要： AC coupling and signal amplification using switched capacitors. The use of a switched capacitor to simulate a resistor in amplifier coupling in an integrated circuit processing audio frequency signals avoids the need for external components, reducing cost and eliminating the need for pinouts for the external components. In a system including an anti-aliasing filter, capacitive coupling is used for coupling between amplifiers, with the gain of the second amplifier being set by a feedback capacitor between the amplifier output and its input, as sized relative to the coupling capacitor. The switched capacitor in the feedback loop of the second amplifier preferably couples the output of the anti-aliasing filter back to the amplifier input, thereby minimizing the aliasing from the capacitor switching.

摘要翻译： 使用开关电容的交流耦合和信号放大。 在集成电路处理音频信号中使用开关电容器来模拟放大器耦合中的电阻器避免了对外部组件的需要，降低了成本并且消除了对外部组件的引脚分配的需要。 在包括抗混叠滤波器的系统中，电容耦合用于放大器之间的耦合，第二放大器的增益由放大器输出端与其输入端之间的反馈电容器相对于耦合电容器的尺寸来设定。 第二放大器的反馈回路中的开关电容器优选地将抗混叠滤波器的输出耦合到放大器输入端，从而使来自电容器切换的混叠最小化。

公开(公告)号：US6100752A

公开(公告)日：2000-08-08

申请号：US928716

申请日：1997-09-12

申请人： May Lee ,  Lawrence D. Engh ,  Hagop Nazarian

发明人： May Lee ,  Lawrence D. Engh ,  Hagop Nazarian

IPC分类号： H02M3/07 ,  H03K3/01

CPC分类号： H02M3/07

摘要： The present invention is a charge pump circuit to reduce and distribute power supply current surges. The charge pump circuit includes a first clock line to provide a first clock thereon, a plurality of delay circuits connected in series, each delay circuit generating a delayed and inverted clock from its input clock on a respective output clock line, and a plurality of charge pump stages connected in series each to store charge thereon. The first clock line is coupled to the first charge pump stage and the plurality of output clock lines are coupled to a respective plurality of remaining charge pump stages. The operation of each charge pump stage is staggered to reduce and distribute the power supply current surges.

摘要翻译： 本发明是一种用于减少和分配电源电流浪涌的电荷泵电路。 电荷泵电路包括：第一时钟线，用于提供第一时钟，串联连接的多个延迟电路，每个延迟电路从相应输出时钟线上的输入时钟产生延迟和反相时钟，以及多个充电 泵级分别串联连接以在其上存储电荷。 第一时钟线耦合到第一电荷泵级，并且多个输出时钟线耦合到相应的多个剩余电荷泵级。 每个电荷泵级的操作是交错的，以减少和分配电源电流浪涌。

公开(公告)号：US5745414A

公开(公告)日：1998-04-28

申请号：US756564

申请日：1996-11-26

申请人： Lawrence D. Engh ,  Trevor Blyth

发明人： Lawrence D. Engh ,  Trevor Blyth

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C27/00 ,  G11C11/34

CPC分类号： G11C27/005 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5624 ,  G11C2211/5642 ,  G11C7/16

摘要： The present invention is an improvement in an analog storage device having a row of EEPROM cells. The improvement includes providing a reference EEPROM cell having first and second transistors connected in series, with a gate of the first transistor connected to a clear input line and a gate of the second transistor connected to a select input line. The improvement further includes providing a comparator having first and second inputs with the first input connected to a source of the second transistor and a second input connected to a reference voltage line and with an output of the comparator connected to the gate of the first transistor, wherein the gate of the first transistor is connected to gates of first transistors of each of the row of EEPROM cells.

摘要翻译： 本发明是具有一行EEPROM单元的模拟存储装置的改进。 该改进包括提供具有串联连接的第一和第二晶体管的参考EEPROM单元，第一晶体管的栅极连接到清零输入线，第二晶体管的栅极连接到选择输入线。 该改进还包括提供具有第一和第二输入的比较器，其中第一输入连接到第二晶体管的源极，第二输入端连接到参考电压线，并且比较器的输出连接到第一晶体管的栅极， 其中所述第一晶体管的栅极连接到所述一行EEPROM单元的每一行的第一晶体管的栅极。

公开(公告)号：US07197299B2

公开(公告)日：2007-03-27

申请号：US10752630

申请日：2004-01-07

申请人： Geoffrey B. Jackson ,  Saleel V. Awsare ,  Lawrence D. Engh ,  Peter Holzmann ,  Oliver C. Kao ,  Carl R. Palmer ,  Aditya Raina

发明人： Geoffrey B. Jackson ,  Saleel V. Awsare ,  Lawrence D. Engh ,  Peter Holzmann ,  Oliver C. Kao ,  Carl R. Palmer ,  Aditya Raina

IPC分类号： H04Q7/22 ,  H04B1/28

CPC分类号： H04M1/725 ,  G11C27/005 ,  H04M1/6041 ,  H04M1/6505

摘要： A multilevel analog recording and playback system is described. The analog recording and playback system provides a variety of analog processing functions to enhance system level integration. The analog recording and playback system is an fully configurable integrated device that includes a plurality of signal paths, a microphone automatic gain control (“AGC”) circuit, volume control and filtering circuit, speaker driver circuit, gain selectable analog input, auxiliary input and output paths, configurable summation amplifiers having mixing features, multilevel analog memory storage array, and user selectable programming duration.

摘要翻译： 描述了多级模拟录音和播放系统。 模拟录音和回放系统提供了各种模拟处理功能，以增强系统级集成度。 模拟录音和回放系统是一个完全可配置的集成设备，包括多个信号路径，麦克风自动增益控制（“AGC”）电路，音量控制和滤波电路，扬声器驱动电路，增益可选模拟输入，辅助输入和 输出路径，具有混合特征的可配置求和放大器，多级模拟存储器存储阵列和用户可选择的编程持续时间。

公开(公告)号：US06301151B1

公开(公告)日：2001-10-09

申请号：US09634180

申请日：2000-08-09

申请人： Lawrence D. Engh ,  Albert V. Kordesch ,  Ping Guo ,  Chun-Mai Liu

发明人： Lawrence D. Engh ,  Albert V. Kordesch ,  Ping Guo ,  Chun-Mai Liu

IPC分类号： G11C700

CPC分类号： G11C16/12 ,  G11C27/005

摘要： Adaptive programming method and apparatus for flash memory analog storage. The present invention method is to adjust the voltage of the programming pulse each time based on the result of the previous pulse. The expected change in the programmed value is compared to the measured change, and the difference used to improve the model of that cell after each programming pulse. The algorithm is “adaptive” because the voltage of each pulse is adapted to whatever the cell needs. If the cell is programming too slowly, the voltage is increased dramatically to make it faster. Conversely if the results show that a particular cell is programming too fast, the next voltage pulse is increased by only a small amount (or even decreased if necessary). Because the response of the cell is non-linear, a special analog circuit is used to calculate the optimum voltage for each pulse. As one alternative, a digital calculation may also be used to program the cells. Because of the programming speed of the exemplary method, a voice signal may be sampled and stored in flash memory one cell at a time. Variable programming parameters other than voltage may be used if desired.

摘要翻译： 闪存模拟存储的自适应编程方法和装置。 本发明的方法是基于先前脉冲的结果每次调节编程脉冲的电压。 将编程值的预期变化与测量的变化进行比较，以及用于在每个编程脉冲之后改善该单元的模型的差异。 该算法是“自适应”的，因为每个脉冲的电压适应于任何单元需要。 如果电池的编程速度太慢，电压会急剧增加，使其更快。 相反，如果结果显示特定的单元格编程速度太快，则下一个电压脉冲仅增加少量（或者如果需要甚至减小）。 由于单元的响应是非线性的，所以使用特殊的模拟电路来计算每个脉冲的最佳电压。 作为一种替代方案，也可以使用数字计算来对单元进行编程。 由于示例性方法的编程速度，一次可以将语音信号采样并存储在闪存中一个单元。 如果需要，可以使用电压以外的可变编程参数。

公开(公告)号：US5986928A

公开(公告)日：1999-11-16

申请号：US924795

申请日：1997-09-05

申请人： Lawrence D. Engh ,  Michael H. Herman

发明人： Lawrence D. Engh ,  Michael H. Herman

IPC分类号： G11C16/06 ,  G10L19/00 ,  G11C27/00 ,  G11C11/34

CPC分类号： G11C27/005

摘要： The present invention is a method of indicating an end of message marker in a plurality of memory cells. The method includes the step of clearing a plurality of memory cells by programming the plurality of memory cells within a first predetermined voltage range to indicate an end of message. The method further includes the step of recording an input signal onto at least a portion of the plurality of memory cells within a second predetermined voltage range. The first and second predetermined voltage ranges are non-overlapping voltage ranges.

摘要翻译： 本发明是指示多个存储单元中消息标记结束的方法。 该方法包括通过在第一预定电压范围内对多个存储单元进行编程来清除多个存储器单元以指示消息结束的步骤。 该方法还包括在第二预定电压范围内将输入信号记录在多个存储单元的至少一部分上的步骤。 第一和第二预定电压范围是不重叠的电压范围。

公开(公告)号：US06882136B2

公开(公告)日：2005-04-19

申请号：US10854657

申请日：2004-05-26

申请人： Hagop A. Nazarian ,  William Tang ,  Zhan Duan ,  Chao-Ming Tsai ,  Lawrence D. Engh

发明人： Hagop A. Nazarian ,  William Tang ,  Zhan Duan ,  Chao-Ming Tsai ,  Lawrence D. Engh

IPC分类号： H03H11/24 ,  H03M1/80 ,  H02J3/12

CPC分类号： H03M1/808 ,  H03H11/245

摘要： An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance element is connected in series in a mirrored configuration about the center impedance element.

摘要翻译： 阻抗网络，其包括至少一个端子端子，擦拭器端子，中心阻抗元件和第一多个阻抗元件。 抽头端子以阻抗网络的选定阻抗值提供抽头位置，可以以指定的增量值进行选择。 第一组多个阻抗元件被配置为在从一个分接位置切换到另一分接头位置时降低电阻变化。 第一组多个阻抗元件以关于中心阻抗元件的镜像配置串联连接。

公开(公告)号：US06788042B2

公开(公告)日：2004-09-07

申请号：US10102117

申请日：2002-03-20

申请人： Hagop A. Nazarian ,  William Tang ,  Zhan Duan ,  Chao-Ming Tsai ,  Lawrence D. Engh

发明人： Hagop A. Nazarian ,  William Tang ,  Zhan Duan ,  Chao-Ming Tsai ,  Lawrence D. Engh

IPC分类号： H02J312

CPC分类号： H03M1/808 ,  H03H11/245

摘要： An impedance network, which includes at least one end terminal, a wiper terminal, a center impedance element, and a first plurality of impedance elements. The wiper terminal provides a tap position at a selected impedance value of the impedance network, selectable at a specified increment value. The first plurality of impedance elements is configured to reduce resistance variation during switching from one tap position to another tap position. The first plurality of impedance elements is connected in series in a mirrored configuration about the center impedance element.

摘要翻译： 阻抗网络，其包括至少一个端子端子，擦拭器端子，中心阻抗元件和第一多个阻抗元件。 抽头端子以阻抗网络的选定阻抗值提供抽头位置，可以以指定的增量值进行选择。 第一组多个阻抗元件被配置为在从一个分接位置切换到另一分接头位置时降低电阻变化。 第一组多个阻抗元件以关于中心阻抗元件的镜像配置串联连接。