Method and apparatus for reducing propagation latency in a high speed
crossbar switch
    1.
    发明授权
    Method and apparatus for reducing propagation latency in a high speed crossbar switch 失效
    降低高速交叉开关中传播延迟的方法和装置

    公开(公告)号:US5896516A

    公开(公告)日:1999-04-20

    申请号:US885821

    申请日:1997-06-30

    CPC分类号: G06F13/4022

    摘要: A protocol and apparatus for crossbar switches where the cycle time is too short to allow the updating of the input/output buffer controls by the arbitration logic in one cycle. The crossbar switch has separate data paths and commands paths. Two types of commands are sent over the crossbar switches. The first type is an address (A) only command which consist of a single packet needing one clock cycle. The second type of command is an Address with Data command (AD), consisting of two through nine packets, and requiring a maximum of nine clock cycles. A command becomes a request through two different paths through the crossbar switch. The first path is via an input bypass path which allows an input command buffer to be bypassed and a request written directly to a multiplexer. The second path is through the input command buffer which is written but not selected until processing is completed for the previous command. The crossbar protocol allows a request to be accepted by writing information into the output buffers before the accept is available.

    摘要翻译: 一种用于交叉开关的协议和装置,其中周期时间太短,从而不能在一个周期内由仲裁逻辑更新输入/输出缓冲器控制。 交叉开关具有单独的数据路径和命令路径。 两种类型的命令通过交叉开关发送。 第一种类型是仅需要一个时钟周期的单个数据包的地址(A)命令。 第二种类型的命令是一个地址数据命令(AD),由两个到九个数据包组成,最多需要九个时钟周期。 命令通过交叉开关的两个不同路径成为一个请求。 第一条路径是通过输入旁路路径,允许输入命令缓冲器被旁路,并将请求直接写入多路复用器。 第二条路径是通过输入命令缓冲区,该缓冲区被写入但不被选择,直到前一个命令的处理完成为止。 交叉开关协议允许在接受可用之前将信息写入输出缓冲器来接受请求。

    Handling denormal floating point operands when result must be normalized
    3.
    发明授权
    Handling denormal floating point operands when result must be normalized 失效
    当结果必须归一化时,处理非正常浮点操作数

    公开(公告)号:US08260837B2

    公开(公告)日:2012-09-04

    申请号:US12234890

    申请日:2008-09-22

    IPC分类号: G06F7/487

    CPC分类号: G06F7/483 G06F7/49936

    摘要: A system for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

    摘要翻译: 当结果必须归一化时,用于处理异常浮点运算的系统。 操作数B(opB)上的前导零计数器(lzc)用于在opB为非正常时限制对准偏移,但是远大于操作数A和C的乘积即AC。 通过在标准化期间限制B的附加偏移,通过opB中的前导零的数量,在对准移位器的输出总线中不需要增加。 此外,附加移位可以在对准移位器中进行,或者延迟到流水线中的后一阶段,其中结果被归一化。

    Handling denormal floating point operands when result must be normalized
    4.
    发明授权
    Handling denormal floating point operands when result must be normalized 失效
    当结果必须归一化时,处理非正常浮点操作数

    公开(公告)号:US07451172B2

    公开(公告)日:2008-11-11

    申请号:US11055046

    申请日:2005-02-10

    IPC分类号: G06F7/483

    CPC分类号: G06F7/483 G06F7/49936

    摘要: A method for handling denormal floating point operands when the result must be normalized. A leading zero counter (lzc) on the operand B (opB) is used to limit alignment shifts when opB is denormal but is much greater than the product of operands A and C, i.e. AC. By limiting the additional shift of B during normalization, by the number of leading zeros in opB, no increase is needed in the output bus of the alignment shifter. Furthermore, the additional shift may be done either in the alignment shifter, or postponed to a later stage in the pipeline, where the result is normalized.

    摘要翻译: 当结果必须被归一化时,用于处理异常浮点操作数的方法。 操作数B(opB)上的前导零计数器(lzc)用于在opB为非正常时限制对准偏移,但是远大于操作数A和C的乘积即AC。 通过在标准化期间限制B的附加偏移,通过opB中的前导零的数量,在对准移位器的输出总线中不需要增加。 此外,附加移位可以在对准移位器中进行,或者延迟到流水线中的后一阶段,其中结果被归一化。

    Computer chip heat responsive method and apparatus
    5.
    发明授权
    Computer chip heat responsive method and apparatus 有权
    计算机芯片热响应方法和装置

    公开(公告)号:US06934658B2

    公开(公告)日:2005-08-23

    申请号:US10401410

    申请日:2003-03-27

    摘要: Disclosed is an apparatus incorporating hardware based logic and a predetermined default list of software affecting responses to be taken in connection with temperatures sensed by thermal sensors checking the temperature of portions of computer logic. At the time application software is loaded, the software can modify the default response list. The list of responses to be taken and the over temperature conditions at which they are to be activated are stored in hardware directly accessible by hardware based thermal sensor monitoring logic for direct control of the hardware. The control can alter conditions such as clock frequency, stopping use of application software, interrupting OS functionality, removing power from components and so forth.

    摘要翻译: 公开了一种装置,其包含基于硬件的逻辑和预期的默认的软件列表,该缺省软件影响与由热传感器检测到的温度有关的响应而被采用,所述热传感器检测计算机逻辑部分的温度。 在应用软件加载的时候,软件可以修改默认的响应列表。 要采用的响应列表和它们被激活的过热条件存储在硬件直接可访问的硬件的热传感器监控逻辑中,以直接控制硬件。 该控件可以改变诸如时钟频率,停止使用应用软件,中断OS功能,从组件中移除电力等等的状况。