公开(公告)号：US20050138499A1

公开(公告)日：2005-06-23

申请号：US10707205

申请日：2003-11-26

申请人： Lawrence Pileggi ,  Chik Yue ,  R. Blanton ,  Thomas Vogels

发明人： Lawrence Pileggi ,  Chik Yue ,  R. Blanton ,  Thomas Vogels

IPC分类号： G01R31/28 ,  G01R31/303

CPC分类号： G01R31/3025 ,  G01R31/2884 ,  G01R31/2889 ,  G01R31/303

摘要： A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an usable portion of the wafer. The antenna system may be formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.

摘要翻译： 用于测试晶片上的集成电路的系统可以包括形成在晶片上的收发器。 系统还可以包括可耦合到收发器的天线系统。 收发器可以形成在晶片上的划线，晶片上的芯片或晶片的可用部分之一中。 天线系统可以形成在与收发器相同的划线中的至少一个或形成在晶片中的至少一个其它划线中。 或者，天线系统可以包括晶片外部的天线。

公开(公告)号：US07325180B2

公开(公告)日：2008-01-29

申请号：US10707205

申请日：2003-11-26

申请人： Lawrence Pileggi ,  Chik Patrick Yue ,  R. Shawn Blanton ,  Thomas Vogels

发明人： Lawrence Pileggi ,  Chik Patrick Yue ,  R. Shawn Blanton ,  Thomas Vogels

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/3025 ,  G01R31/2884 ,  G01R31/2889 ,  G01R31/303

摘要： A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an otherwise unusable portion of the wafer. The antenna system maybe formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.

摘要翻译： 用于测试晶片上的集成电路的系统可以包括形成在晶片上的收发器。 系统还可以包括可耦合到收发器的天线系统。 收发器可以形成在晶片上的划线，晶片上的芯片或晶片的其它不可用部分之一中。 天线系统可以形成在与收发器相同的划线中的至少一个或形成在晶片中的至少一个其它划线中。 或者，天线系统可以包括晶片外部的天线。

公开(公告)号：US07487486B2

公开(公告)日：2009-02-03

申请号：US11629445

申请日：2005-06-11

申请人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

发明人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

IPC分类号： G06F17/50 ,  G06F7/60 ,  G06F7/52

CPC分类号： G06F17/5031 ,  G06F2217/10

摘要： The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

摘要翻译： 目前的纳米尺度IC的大规模工艺和环境变化需要用于时序分析和优化的统计方法（1）。 最近重点研究重点是开发新的统计时序分析算法（2），但往往不考虑如何解释统计时序结果进行优化。 本发明提供了一种基于灵敏度的度量（2）来评估统计时序图（4）中每个路径和/或弧的关键性。 定义了路径和弧线的统计灵敏度。 显示路径灵敏度等于路径关键的概率，弧敏感度等于弧位于关键路径上的概率。 描述了具有增量分析能力的有效算法（2），用于快速灵敏度计算，其电路尺寸具有线性运行时间复杂度。 提出的灵敏度分析的功效在标准基准电路和大型行业实例中得到证明。

公开(公告)号：US20070019447A1

公开(公告)日：2007-01-25

申请号：US11176055

申请日：2005-07-07

申请人： Gokce Keskin ,  Xin Li ,  Lawrence Pileggi

发明人： Gokce Keskin ,  Xin Li ,  Lawrence Pileggi

IPC分类号： H02H7/10

CPC分类号： H03K19/00361 ,  H01L27/0288 ,  H03K17/165

摘要： Active resistors for reduction of transient power grid noise. An active resistance added in parallel to the operating circuit blocks of a semiconductor device. This resistance increases the damping ratio of the power grid, which in turn decreases the number and the magnitude of oscillations and/or noise resulting from step disturbances of the power supply current. The active resistance can implemented by a transistor connected to a bias voltage. Alternatively, the active resistance can be implemented by a drive transistor with a gain stage, or two active resistors where one responds to overshoots in the current flow and the second active resistor responds to droops in the current flow.

摘要翻译： 用于减少瞬态电网噪声的有源电阻。 与半导体器件的工作电路块并联的有源电阻。 该电阻增加了电力网的阻尼比，而电网的阻尼比又降低了由电源电流的阶跃扰动引起的振荡和/或噪声的数量和幅度。 有源电阻可以由连接到偏置电压的晶体管实现。 或者，有源电阻可以由具有增益级的驱动晶体管或两个有源电阻器来实现，其中一个响应于电流中的过冲而第二有效电阻器响应电流中的下降。

公开(公告)号：US20080072198A1

公开(公告)日：2008-03-20

申请号：US11629445

申请日：2005-06-11

申请人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

发明人： Mustafa Celik ,  Jiayong Le ,  Lawrence Pileggi ,  Xin Li

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10

摘要： The large-scale process and environmental variations for today's nano-scale ICs are requiring statistical approaches for timing analysis and optimization (1). Significant research has been recently focused on developing new statistical timing analysis algorithms (2), but often without consideration for how one should interpret the statistical timing results for optimization. The invention provides a sensitivity-based metric (2) to assess the criticality of each path and/or arc in the statistical timing graph (4). The statistical sensitivities for both paths and arcs are defined. It is shown that path sensitivity is equivalent to the probability that a path is critical, and arc sensitivity is equivalent to the probability that an arc sits on the critical path. An efficient algorithm with incremental analysis capability (2) is described for fast sensitivity computation that has a linear runtime complexity in circuit size. The efficacy of the proposed sensitivity analysis is demonstrated on both standard benchmark circuits and large industry examples.

摘要翻译： 目前的纳米尺度IC的大规模工艺和环境变化需要用于时序分析和优化的统计方法（1）。 最近重点研究重点是开发新的统计时序分析算法（2），但往往不考虑如何解释统计时序结果进行优化。 本发明提供了一种基于灵敏度的度量（2）来评估统计时序图（4）中每个路径和/或弧的关键性。 定义了路径和弧线的统计灵敏度。 显示路径灵敏度等于路径关键的概率，弧敏感度等于弧位于关键路径上的概率。 描述了具有增量分析能力的有效算法（2），用于快速灵敏度计算，其电路尺寸具有线性运行时间复杂度。 提出的灵敏度分析的功效在标准基准电路和大型行业实例中得到证明。

公开(公告)号：US20060047491A1

公开(公告)日：2006-03-02

申请号：US11208844

申请日：2005-08-22

申请人： Xin Li ,  Yang Xu ,  Peng Li ,  Lawrence Pileggi

发明人： Xin Li ,  Yang Xu ,  Peng Li ,  Lawrence Pileggi

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： Analog and radio frequency system-level simulation using frequency relaxation. Embodiments of the invention use a frequency relaxation approach for analog/RF system-level simulation that accommodates both large system size and complex signal space. The simulator can determine an output response for a system by partitioning the system into blocks and simulating the propagation of an input signal through the blocks. The input signal can take various forms, including a multi-tone sinusoidal signal, a continuous spectra signal, and/or a stochastic signal. Frequency relaxation is applied to produce individual responses. The output response can be computed based on obtaining convergence of the individual responses. The input to embodiments of the simulator can be a circuit netlist, or a block-level macromodel.

摘要翻译： 模拟和射频系统级仿真使用频率弛豫。 本发明的实施例使用容纳大系统尺寸和复杂信号空间的模拟/ RF系统级仿真的频率松弛方法。 模拟器可以通过将系统划分成块并且模拟通过块的输入信号的传播来确定系统的输出响应。 输入信号可以采取各种形式，包括多音频正弦信号，连续频谱信号和/或随机信号。 应用频率弛豫来产生个体反应。 可以基于获得各个响应的收敛来计算输出响应。 模拟器的实施例的输入可以是电路网表或块级宏模型。

公开(公告)号：US06961916B2

公开(公告)日：2005-11-01

申请号：US10136161

申请日：2002-05-01

申请人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

发明人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

公开(公告)号：US06651232B1

公开(公告)日：2003-11-18

申请号：US09186430

申请日：1998-11-05

申请人： Lawrence Pileggi ,  Christopher Dunn ,  Satyamurthy Pullela ,  Majid Sarrafzadeh ,  Tong Gao ,  Salil Raje

发明人： Lawrence Pileggi ,  Christopher Dunn ,  Satyamurthy Pullela ,  Majid Sarrafzadeh ,  Tong Gao ,  Salil Raje

IPC分类号： G06F1750

CPC分类号： G06F1/10 ,  G06F17/5077

摘要： Progressively optimized clock tree/mesh construction is performed concurrently with placement of all remaining objects. Clock tree/mesh is specified loosely for initial placement, then followed by progressive detailed placement. In particular, preferred approach provides automated and reliable solution to clock tree/mesh construction, occuring concurrently with placement process so that clock tree wiring and buffering considers and influences placement and wiring of all other objects, such as logic gates, memory elements, macrocells, etc. Hence, in this concurrent manner, clock tree/mesh pre-wiring and pre-buffering may be based on construction of approximate clock tree using partitioning information only, i.e., prior to object placement. Further, present approach provides modified DME-based clock tree topology construction without meandering, and recursive algorithm for buffered clock tree construction.

摘要翻译： 逐渐优化的时钟树/网格构建与所有剩余对象的放置同时执行。 时钟树/网格被松散地指定用于初始放置，然后是渐进的详细放置。 特别地，优选的方法为时钟树/网格构造提供了自动化和可靠的解决方案，与布置过程同时发生，使得时钟树布线和缓冲考虑并影响所有其他对象（诸如逻辑门，存储器元件，宏单元）的布局和布线， 因此，以这种并发方式，时钟树/网格预接线和预缓冲可以基于仅使用分区信息（即，在对象放置之前）构建近似时钟树。 此外，目前的方法提供了基于改进的基于DME的时钟树拓扑构造而不进行曲折，并且缓冲时钟树构建的递归算法。

公开(公告)号：US06367051B1

公开(公告)日：2002-04-02

申请号：US09096810

申请日：1998-06-12

申请人： Lawrence Pileggi ,  Sharad Malik ,  Emre Tuncer ,  Abhijeet Chakraborty ,  Satyamurthy Pullela ,  Altan Odabasioglu ,  Douglas B. Boyle

发明人： Lawrence Pileggi ,  Sharad Malik ,  Emre Tuncer ,  Abhijeet Chakraborty ,  Satyamurthy Pullela ,  Altan Odabasioglu ,  Douglas B. Boyle

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A design tool for integrated circuits includes a placement tool which concurrently places logic gates and interconnect. In one embodiment, the logic gates are placed into bins and virtual buffers are inserted between logic gates mapped to different bins. Placement and interconnect wire lengths and densities are successively improved leading to removal of some buffers and actualization of the virtual buffers.

摘要翻译： 用于集成电路的设计工具包括同时放置逻辑门和互连的放置工具。 在一个实施例中，逻辑门被放置到存储区中，并且虚拟缓冲器被插入映射到不同仓的逻辑门之间。 放置和互连线长度和密度被连续改善，导致一些缓冲器的移除和虚拟缓冲器的实现。

公开(公告)号：US06192508B1

公开(公告)日：2001-02-20

申请号：US09097076

申请日：1998-06-12

申请人： Sharad Malik ,  Lawrence Pileggi ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Douglas B. Boyle

发明人： Sharad Malik ,  Lawrence Pileggi ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Douglas B. Boyle

IPC分类号： G06F1750

CPC分类号： G06F17/505 ,  G06F17/5072

摘要： This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.

摘要翻译： 本发明认识到逻辑优化能够帮助放置缓解拥塞。 使用不同类型的逻辑优化来帮助放置缓解拥塞。 在一种类型的优化中，通过选择更快的单元来提高电路部分的速度。 在另一种类型的优化中，改变电路的拓扑结构，使得放置现在可以移动以前不能被移动的单元，以减少拥塞并由此实现路由。 该方法的一个突出特点是，它不仅在逻辑优化期间使用放置信息进行互连延迟/面积估计，而且还通过为放置提供支持来使用逻辑优化来辅助物理放置步骤，从而改善电路的拥塞 。 目的是避免进入放置的电路不能路由的情况。