公开(公告)号：US5847600A

公开(公告)日：1998-12-08

申请号：US638287

申请日：1996-04-26

申请人： Todd L. Brooks ,  Lawrence Singer

发明人： Todd L. Brooks ,  Lawrence Singer

IPC分类号： H03F3/00 ,  H03F3/45 ,  H03F3/72

CPC分类号： H03F3/4521 ,  H03F3/005 ,  H03F3/45188 ,  H03F3/45242 ,  H03F3/72 ,  H03F2203/45356 ,  H03F2203/45644 ,  H03F2203/45651 ,  H03F2203/45682

摘要： A two-stage switched-capacitor residue amplifier having novel circuitry in the first and second stages provides fast and accurate settling while configured with a large closed-loop gain, and also provides low power consumption while powered from a five volt supply. The invention is particularly well suited for use in a multi-stage, pipe-lined analog-to-digital converter (ADC) that converts multiple bits in the first pipeline stage. Complementary PMOS and NMOS differential pairs are used in the first and/or second stage to increase the current slew capability of the amplifier. Current mirror gain and/or positive feedback is used in the second stage to increase transonductance and bandwidth. Cascode transistors are used in the output of the first and/or second stages and active cascode gain enhancement is used in the first stage to increase dc gain and accuracy. The common mode level at the output of the second stage is controlled by injecting a pair of control currents (representative of the difference between a common-mode level actually at the output of the second stage and a desired common mode level) into a pair of mirror input nodes in the second stage. The common mode level of the first stage is controlled from a common node of a differential pair of the second stage. The two-stage amplifier of the invention provides a gain bandwidth product of 800 MHz, a closed-loop bandwidth of 50 MHz, a dc gain 90 dB, and a power consumption 80 mW.

摘要翻译： 在第一和第二阶段具有新颖电路的两级开关电容器残余放大器提供快速和准确的稳定，同时配置有大的闭环增益，并且在由五伏电源供电时也提供低功耗。 本发明特别适用于在第一流水线级中转换多个比特的多级管线模数转换器（ADC）。 互补PMOS和NMOS差分对用于第一和/或第二级以增加放大器的电流转换能力。 在第二阶段使用电流镜增益和/或正反馈来增加电导率和带宽。 串级晶体管用于第一级和/或第二级的输出，并且在第一级中使用有源共源共轭增益增强以增加直流增益和精度。 第二级输出端的共模电平通过将一对控制电流（代表第二级输出端的共模电平与期望的共模电平之间的差）代入一对 第二阶段的镜像输入节点。 第一级的共模级由第二级的差分对的公共节点控制。 本发明的两级放大器提供800MHz的增益带宽乘积，50MHz的闭环带宽，直流增益90dB，功耗80mW。

公开(公告)号：US5789981A

公开(公告)日：1998-08-04

申请号：US638195

申请日：1996-04-26

申请人： Lawrence Singer ,  Todd L. Brooks

发明人： Lawrence Singer ,  Todd L. Brooks

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/3001 ,  H03F2203/30096 ,  H03F2203/30129

摘要： A high-gain, low-power transconductance amplifier suitable for use in switched-capacitor circuits provides improved accuracy and high-speed operation. The transconductance amplifier includes an input circuit that receives an input voltage. A current mirror circuit is coupled to the input circuit. At least one active cascode circuit, coupled to the current mirror circuit, receives current from the current mirror circuit and provides an output current. The active cascode circuit provides gain enhancement to the transconductance amplifier by increasing the output impedance of the transconductance amplifier.

摘要翻译： 适用于开关电容电路的高增益，低功耗跨导放大器提供更高的精度和高速运行。 跨导放大器包括接收输入电压的输入电路。 电流镜电路耦合到输入电路。 耦合到电流镜电路的至少一个有源共源共栅电路从电流镜电路接收电流并提供输出电流。 有源共源共栅电路通过增加跨导放大器的输出阻抗来为跨导放大器提供增益增益。

公开(公告)号：US5854574A

公开(公告)日：1998-12-29

申请号：US639208

申请日：1996-04-26

申请人： Lawrence Singer ,  Todd L. Brooks

发明人： Lawrence Singer ,  Todd L. Brooks

IPC分类号： H03F3/30 ,  H03F3/45 ,  H03F1/34 ,  H03F1/42

CPC分类号： H03F3/45659 ,  H03F3/3028 ,  H03F3/45183 ,  H03F3/45946 ,  H03F2203/45068 ,  H03F2203/45216 ,  H03F2203/45352 ,  H03F2203/45508 ,  H03F2203/45644 ,  H03F2203/45658

摘要： A reference buffer suitable for driving switched-capacitor or resistive load circuits provides a very low output impedance. The reference buffer utilizes an amplifier with a very large and controlled transconductance configured in feedback and compensated by a load capacitance. Cascaded gain stages are used to provide a large, controlled transconductance. In one embodiment, a reference buffer amplifier includes a plurality of voltage gain amplifiers connected in cascade and at least one transconductance amplifier connected to a last-connected of the plurality of voltage gain amplifiers. The amplifier may further include at least one current mirror amplifier connected to the at least one transconductance amplifier. In another embodiment, the reference buffer amplifier includes at least one transconductance amplifier and at least one current mirror amplifier cascade-connected to the at least one transconductance amplifier. The amplifiers can be differential or single-ended.

摘要翻译： 适用于驱动开关电容或电阻负载电路的参考缓冲器提供非常低的输出阻抗。 参考缓冲器使用具有非常大的和受控跨导的放大器，其配置为反馈并由负载电容补偿。 级联增益级用于提供大的受控跨导。 在一个实施例中，参考缓冲放大器包括串联连接的多个电压增益放大器和连接到多个电压增益放大器的最后连接的至少一个跨导放大器。 放大器还可以包括连接到至少一个跨导放大器的至少一个电流镜放大器。 在另一个实施例中，参考缓冲放大器包括至少一个跨导放大器和与至少一个跨导放大器级联连接的至少一个电流镜放大器。 放大器可以是差分或单端。

公开(公告)号：US08829979B2

公开(公告)日：2014-09-09

申请号：US12807610

申请日：2010-09-08

申请人： Sherif Galal ,  Tay Hui Zheng ,  Todd L. Brooks

发明人： Sherif Galal ,  Tay Hui Zheng ,  Todd L. Brooks

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： H02M3/07

摘要： Disclosed is a power-efficient multi-mode charge pump. The charge pump comprises a first pumping circuit that provides at least one output voltage produced by a discharge sequence of a shared flyback capacitor. The charge pump also comprises a second pumping circuit that provides a plurality of output voltages produced by a corresponding plurality of discharge sequences of the shared flyback capacitor. The charge pump may include a transition circuit to selectably enable the first pumping circuit or the second pumping circuit. In one embodiment, the first pumping circuit may employ a two-phase discharge sequence. In another embodiment, the second pumping circuit may employ a three-phase plurality of discharge sequences. A related method is also disclosed.

摘要翻译： 公开了一种功率高效的多模式电荷泵。 电荷泵包括提供由共享回扫电容器的放电序列产生的至少一个输出电压的第一泵浦电路。 电荷泵还包括第二泵浦电路，其提供由共享回扫电容器的相应多个放电序列产生的多个输出电压。 电荷泵可以包括可选择地使第一泵送电路或第二泵浦电路的转换电路。 在一个实施例中，第一泵浦电路可采用两相放电序列。 在另一个实施例中，第二泵浦电路可以采用三相多个放电序列。 还公开了相关方法。

公开(公告)号：US08294518B2

公开(公告)日：2012-10-23

申请号：US12807403

申请日：2010-09-03

申请人： Sherif Galal ,  Alex Jianzhong Chen ,  Khaled Abdelfattah ,  Todd L. Brooks

发明人： Sherif Galal ,  Alex Jianzhong Chen ,  Khaled Abdelfattah ,  Todd L. Brooks

IPC分类号： H03F3/26

CPC分类号： H03F3/211 ,  H03F1/301 ,  H03F3/3022 ,  H03F2200/375 ,  H03F2200/453 ,  H03F2203/30015

摘要： Disclosed is a Class-AB/B amplifier comprising a first output stage including a first plurality of amplification devices and a second output stage including a second plurality of amplification devices. According to one embodiment, the first output stage operates when the Class-AB/B amplifier is in a quiescent state and the second output stage operates when the Class-AB/B amplifier is in an active state. The Class-AB/B amplifier also comprises a level shifting circuit that adjusts a control voltage of the second output stage, where the level shifting circuit is adapted to activate the second output stage when the Class-AB/B amplifier enters the active state. Embodiments of the Class-AB/B amplifier may include a level shifting circuit that implements either a fixed or signal-dependent level shift, and a quiescent control circuit that substantially eliminates any systematic offset arising from the active feedback circuit inside the replica bias circuit.

摘要翻译： 公开了一种AB-B类放大器，其包括包括第一多个放大装置的第一输出级和包括第二多个放大装置的第二输出级。 根据一个实施例，当AB类/ B放大器处于静态时，第一输出级工作，而当AB类/ B放大器处于活动状态时，第二输出级工作。 AB类/ B放大器还包括一个电平移动电路，其调节第二输出级的控制电压，其中当AB类/ B放大器进入激活状态时，电平移位电路用于激活第二输出级。 AB类/ B放大器的实施例可以包括实现固定或信号相关电平移位的电平移位电路和基本上消除由复制偏置电路内部的有源反馈电路产生的任何系统偏移的静态控制电路。

公开(公告)号：US08237496B2

公开(公告)日：2012-08-07

申请号：US12804834

申请日：2010-07-29

申请人： Xicheng Jiang ,  Jungwoo Song ,  Minsheng Wang ,  Todd L. Brooks

发明人： Xicheng Jiang ,  Jungwoo Song ,  Minsheng Wang ,  Todd L. Brooks

IPC分类号： H03F3/38

CPC分类号： H03F3/217

摘要： Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.

摘要翻译： 公开了具有增强的电源抑制的开关放大器。 开关放大器包括提供调制信号的数字调制器。 开关放大器还包括耦合到数字调制器的闭环模拟驱动器。 如所公开的，闭环模拟驱动器被配置为重新调制对应于调制信号的调制信号。 开关放大器的输出级由再调制信号驱动，从而提供增强的电源抑制。 在一个实施例中，调制信号由D类放大器的数字脉冲宽度调制器（PWM）电路产生，并且具有基本上小于数字PWM电路的时钟速率的脉冲速率。 在一个实施例中，开关放大器被实现为诸如蜂窝电话的移动通信设备中的音频放大器。

公开(公告)号：US20110204961A1

公开(公告)日：2011-08-25

申请号：US12807610

申请日：2010-09-08

申请人： Sherif Galal ,  Tay Hui Zheng ,  Todd L. Brooks

发明人： Sherif Galal ,  Tay Hui Zheng ,  Todd L. Brooks

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： Disclosed is a power-efficient multi-mode charge pump. The charge pump comprises a first pumping circuit that provides at least one output voltage produced by a discharge sequence of a shared flyback capacitor. The charge pump also comprises a second pumping circuit that provides a plurality of output voltages produced by a corresponding plurality of discharge sequences of the shared flyback capacitor. The charge pump may include a transition circuit to selectably enable the first pumping circuit or the second pumping circuit. In one embodiment, the first pumping circuit may employ a two-phase discharge sequence. In another embodiment, the second pumping circuit may employ a three-phase plurality of discharge sequences. A related method is also disclosed.

摘要翻译： 公开了一种功率高效的多模式电荷泵。 电荷泵包括提供由共享回扫电容器的放电序列产生的至少一个输出电压的第一泵浦电路。 电荷泵还包括第二泵浦电路，其提供由共享回扫电容器的相应多个放电序列产生的多个输出电压。 电荷泵可以包括可选择地使第一泵送电路或第二泵浦电路的转换电路。 在一个实施例中，第一泵浦电路可采用两相放电序列。 在另一个实施例中，第二泵浦电路可以采用三相多个放电序列。 还公开了相关方法。

公开(公告)号：US20100117685A1

公开(公告)日：2010-05-13

申请号：US12268305

申请日：2008-11-10

申请人： Hongwei Kong ,  Nelson Sollenberger ,  Todd L. Brooks ,  Yee Ling Cheung ,  Xicheng Jiang

发明人： Hongwei Kong ,  Nelson Sollenberger ,  Todd L. Brooks ,  Yee Ling Cheung ,  Xicheng Jiang

IPC分类号： H03K5/22

CPC分类号： G06F13/4072

摘要： Aspects of a method and system for detecting and identifying electronic accessories or peripherals utilizing a hardware audio CODEC are provided. In this regard, a hardware audio CODEC may be operable to compare one or more voltages on one or more biased pins of an accessory or peripheral port to one or more reference voltages and generate one or more digital representations of the one or more voltages on the biased one or more pins. An accessory or peripheral attached to the accessory or peripheral port may be identified based on the comparison and/or the generated one or more digital representations. The one or more bias voltages may be controlled based on a result of the comparison and/or the generated digital representations. The one or more bias voltages may be reduced after an attached accessory or peripheral has been identified.

摘要翻译： 提供了利用硬件音频CODEC来检测和识别电子附件或外围设备的方法和系统的方面。 在这方面，硬件音频编解码器可以用于将附件或外围端口的一个或多个偏置引脚上的一个或多个电压与一个或多个参考电压进行比较，并且生成一个或多个电压的一个或多个数字表示 偏置一个或多个引脚。 可以基于比较和/或所生成的一个或多个数字表示来识别附接到附件或外围端口的附件或外围设备。 可以基于比较的结果和/或所生成的数字表示来控制一个或多个偏置电压。 在附加附件或外围设备被识别之后，可以减小一个或多个偏置电压。

公开(公告)号：US07593483B2

公开(公告)日：2009-09-22

申请号：US11124394

申请日：2005-05-09

申请人： Todd L. Brooks ,  Kevin L. Miller ,  Josephus A. Van Engelen

发明人： Todd L. Brooks ,  Kevin L. Miller ,  Josephus A. Van Engelen

IPC分类号： H03K9/00 ,  H03H7/30 ,  H03M1/00

CPC分类号： H03M7/3013

摘要： In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

摘要翻译： 在高保真数字调制器中，提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声，抖动和串扰。 映射器从量化器接收量化电平，并将量化电平映射到输出序列。 映射器包括定义对应于每个量化级别的多个序列的表。 每个序列包括具有多个值之一的两个或多个符号。 映射器还包括选择多个序列之一作为输出序列的发生器。 第一个输出序列的最后一个符号等于下一个输出序列的第一个符号，依此类推。 发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。 发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。

公开(公告)号：US06934176B2

公开(公告)日：2005-08-23

申请号：US10916606

申请日：2004-08-12

申请人： Khim L. Low ,  Todd L. Brooks ,  Agnes Woo ,  Akira Ito

发明人： Khim L. Low ,  Todd L. Brooks ,  Agnes Woo ,  Akira Ito

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C17/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.