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1.发明授权公开(公告)号：US06643756B1
公开(公告)日：2003-11-04
申请号：US09438308
申请日：1999-11-11
IPC分类号： G06F1200
CPC分类号： G06F3/14 , G06F12/1027 , G06F12/1081
摘要： A request for video or graphics data is made to a memory controller. When the memory controller determines a translation of the data must first be made, a request is made to a translator. The translator either translates the address or requests translation information from the memory controller. The memory controller accesses memory based upon the translator request. If the request is for translation data the results are tagged for the translator. If the translator request is for the translated address, the results are tagged for the original request.
摘要翻译： 对存储器控制器进行视频或图形数据的请求。 当存储器控制器确定首先需要进行数据的转换时，向翻译器发出请求。 翻译器翻译来自存储器控制器的地址或请求翻译信息。 存储器控制器根据翻译器请求访问存储器。 如果请求用于翻译数据，则结果将被标记为翻译器。 如果翻译请求是用于翻译的地址，结果将被标记为原始请求。
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2.发明授权Method of configuring, controlling, and accessing a bridge and apparatus therefor 有权配置，控制和访问其桥及其设备的方法公开(公告)号：US06728820B1
公开(公告)日：2004-04-27
申请号：US09579006
申请日：2000-05-26
申请人： Lee Brian , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
发明人： Lee Brian , Indra Laksono , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Milivoje Aleksic
IPC分类号： G06F1336
CPC分类号： G06F3/14
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换。
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公开(公告)号：US07929648B2
公开(公告)日：2011-04-19
申请号：US11278221
申请日：2006-03-31
IPC分类号： H04L27/06
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译： 错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示 硬连线值和第二个硬连线值到时钟信号。 如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。 时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。
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公开(公告)号：US20070230647A1
公开(公告)日：2007-10-04
申请号：US11278221
申请日：2006-03-31
IPC分类号： H04L7/00
CPC分类号： H04L7/0083
摘要： An error detection apparatus and method compares a first hardwired value such as a first clock threshold, and a second hardwired value such as a second clock threshold, and generates an indication that there is an error in a clock signal based on a comparison of the first hardwired value and the second hardwired value to the clock signal. If an error is detected, the error detection apparatus will, for example, interrupt clock recovery logic to take proper action for recovery of a clock generation circuit that generated the clock signal. The clock signal may be generated based on, for example, a reference clock signal that may be provided by an external source clock, or any other suitable source.
摘要翻译： 错误检测装置和方法比较第一硬连线值（例如第一时钟阈值）和第二硬连线值（例如第二时钟阈值），并且基于第一时钟阈值的比较生成时钟信号中存在错误的指示 硬连线值和第二个硬连线值到时钟信号。 如果检测到错误，则错误检测装置将例如中断时钟恢复逻辑以采取适当的动作来恢复生成时钟信号的时钟产生电路。 时钟信号可以基于例如可由外部源时钟提供的参考时钟信号或任何其它合适的源来产生。
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公开(公告)号：US06532525B1
公开(公告)日：2003-03-11
申请号：US09675368
申请日：2000-09-29
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G09G5/39 , Y02D10/14
摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M commands per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data at a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four-times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.
摘要翻译： 公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。 数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。 响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。 响应于存储器桥请求，多个存储器将以第二数据速率访问多个数据。 当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。 噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。
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公开(公告)号：US06502173B1
公开(公告)日：2002-12-31
申请号：US09675293
申请日：2000-09-29
IPC分类号： G06F1200
CPC分类号： G06F13/1689 , G06F13/1605 , Y02D10/14
摘要： A specific embodiment is disclosed for a method and apparatus for processing data access requests from a requesting device, such as a graphics processor device. Data access commands are provided at a first rate, for example 200M command per second, to a memory bridge. In response to receiving the access requests the memory bridge will provide its own access requests to a plurality of memories at approximately the first rate. In response to the memory bridge requests, the plurality of memories will access a plurality of data a second data rate. When the data access between the memory bridge and the memories is a read request, data is returned to the requesting device at a third data rate which is greater than the first data rate by approximately four times or more. Noise and power reduction techniques can be used on the data bus between the accessing device and the data bridge.
摘要翻译： 公开了一种用于处理来自请求设备（诸如图形处理器设备）的数据访问请求的方法和设备的具体实施例。 数据访问命令以第一速率（例如每秒200M命令）提供给存储器桥。 响应于接收到访问请求，存储器桥将以大约第一速率向多个存储器提供其自己的访问请求。 响应于存储器桥请求，多个存储器将访问多个数据第二数据速率。 当存储器桥和存储器之间的数据访问是读取请求时，数据以大于第一数据速率的大约四倍或更多的第三数据速率返回给请求设备。 噪声和功率降低技术可以在接入设备和数据桥之间的数据总线上使用。
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公开(公告)号：US07543101B2
公开(公告)日：2009-06-02
申请号：US10075149
申请日：2002-02-14
IPC分类号： G06F13/36
CPC分类号： G06T1/60 , G06F13/1663 , G06F13/1684 , G06F13/28 , G06T1/20 , G09G5/39 , G09G5/393 , G09G2360/125
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。
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公开(公告)号：US07017053B2
公开(公告)日：2006-03-21
申请号：US10083917
申请日：2002-02-27
申请人： Carl Mizuyabu , Charles Leung , Milivoje Aleksic
发明人： Carl Mizuyabu , Charles Leung , Milivoje Aleksic
IPC分类号： G06F1/32
CPC分类号： G09G5/006 , G06F1/3203 , G06F1/3218 , G06F1/3225 , G06F1/3237 , G06F1/3265 , G09G5/00 , G09G2330/021 , Y02D10/128 , Y02D10/153
摘要： A system and method are provided for reducing power consumption within a video processing portion of a system based on display content. Display content is monitored to determine whether the display content is changing. New display content is compared to old display content to determine if the display content is changing. If the display content has not changed, a frame rate used to output display data is reduced. A color depth associated with the display data is also reduced. Power consumption can be reduced when it is determined that display content is not changing.
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9.发明授权Apparatus for providing data to a plurality of graphics processors and method thereof 有权用于向多个图形处理器提供数据的装置及其方法公开(公告)号：US06633296B1
公开(公告)日：2003-10-14
申请号：US09579432
申请日：2000-05-26
申请人： Indra Laksono , Milivoje Aleksic , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
发明人： Indra Laksono , Milivoje Aleksic , Antonio Asaro , Andrew E. Gruber , Gordon Caruk , Brian Lee
IPC分类号： G06F1516
CPC分类号： G06F3/14 , G09G5/363 , G09G2352/00 , G09G2360/06
摘要： In a specific embodiment, a system for providing video is disclosed, the system having a system bus, which in one embodiment is an Advanced Graphics Port (AGP) bus. The system bus is connected to a data bridge, which is connected to a second and third AGP bus. Each of the AGP busses are connected to graphics processors. The bridge routes data requests from one graphics processor to the second graphics processor without accessing the system AGP bus based upon a memory mapping information stored in a routing table or a register set. In another aspect of the present invention, the bridge responds to initialization requests using attributes that may vary depending on the specific mode of operation. Another aspect of the present invention allows for conversion between various AGP protocol portions.
摘要翻译： 在具体实施例中，公开了一种用于提供视频的系统，该系统具有系统总线，其在一个实施例中是高级图形端口（AGP）总线。 系统总线连接到连接到第二和第三AGP总线的数据桥。 每个AGP总线都连接到图形处理器。 桥接器基于存储在路由表或寄存器组中的存储器映射信息，将数据请求从一个图形处理器路由到第二图形处理器而不访问系统AGP总线。 在本发明的另一方面，桥接器使用可以根据特定操作模式而变化的属性来响应初始化请求。 本发明的另一方面允许在各种AGP协议部分之间进行转换
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公开(公告)号：US06546449B1
公开(公告)日：2003-04-08
申请号：US09347201
申请日：1999-07-02
IPC分类号： G06F1336
CPC分类号： G06F13/1684
摘要： A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.
摘要翻译： 中央处理器单元（CPU）连接到通常包括单片半导体器件的系统/图形控制器。 系统/图形控制器通过高速PCI总线连接到输入输出（IO）控制器。 IO控制器通过高速PCI总线与系统图形控制器接口。 IO控制器包括由IO控制器内的仲裁器控制的低速PCI端口。 通常，IO控制器的低速PCI仲裁器将与标准的33 MHz PCI卡接口。 此外，IO控制器通过标准或专用总线协议与外部存储设备（如硬盘驱动器）进行接口。 由系统/图形控制器访问的统一的系统/图形存储器。 统一存储器包含系统数据和图形数据。 在具体实施例中，两个通道CH0和CH1访问统一存储器。 每个通道能够访问包含图形数据的存储器的一部分或包含系统数据的存储器的一部分。 因此，每个通道可以同时访问图形数据，同时访问系统数据，或同时访问图形和系统数据。 通过确保将物理地址划分为统一存储器内的块来实现同时访问，这样的数据块是相邻的块被不同的信道访问。
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