公开(公告)号：US5351067A

公开(公告)日：1994-09-27

申请号：US733766

申请日：1991-07-22

申请人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers ,  John L. Pittas

发明人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers ,  John L. Pittas

IPC分类号： G09G5/06 ,  G06T3/00 ,  G06T11/20 ,  G09G5/14 ,  G09G5/36 ,  G09G5/395 ,  H04N5/265 ,  H04N5/272 ,  G09G1/02 ,  G09G1/06

CPC分类号： H04N5/272 ,  G09G5/14 ,  G09G5/395 ,  G09G2340/125

摘要： Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.

摘要翻译： 用于实现提供多个图像的任意混合的光栅图形显示视频数据路径的方法和装置。 视频数据路径是高度并行化的，并且采用在一组查找表的控制下操作的并行设备。 查找表可以从控制器（如主机工作站）加载。 栅格图形显示视频数据路径具有无限的屏幕分辨率，并且还可以从潜在的大量不同的源启用各种不同的像素数据格式。 来自多个图像源的输出在主机工作站的控制下混合，所得到的像素值基于（a）每个图像源的图像的组合半透明系数（α），以及（b）窗口识别号 由主机工作站分配。 将像素值转换为公共预定格式提供了由诸如HDTV和图形服务器之类的多个不同图像源产生的像素值之间的一致性。 为每个源分配单独的帧缓冲区。

公开(公告)号：US5296936A

公开(公告)日：1994-03-22

申请号：US734383

申请日：1991-07-22

申请人： John L. Pittas ,  Sung M. Choi ,  Leon Lumelsky ,  Alan W. Peevers

发明人： John L. Pittas ,  Sung M. Choi ,  Leon Lumelsky ,  Alan W. Peevers

IPC分类号： G06F13/00 ,  G06F15/16 ,  G06F15/173 ,  G06T1/00 ,  G06T1/60 ,  G09B5/14 ,  H04L12/40 ,  H04L12/42 ,  H04N1/00 ,  H04N1/46 ,  H04N5/00 ,  H04N7/00

CPC分类号： G09B5/14 ,  G06F15/17337

摘要： A high-speed communications network (10) provides singlecast, multicast, or broadcast image data capability and is implemented utilizing the High-Performance Parallel Interface (HPPI) as a physical channel. A server (12) includes both a HPPI receiver and transmitter. Workstations (18) support a HPPI-compatible receiver (14b), but require only a simplified HPPI output port (20). The workstations are connected such the receiver port of each is driven by data and control signals from an upstream server HPPI transmitter port. Handshaking signals, generated by the receiver ports, ripple upstream to the server or to an upstream workstation output port. A packet of data bursts corresponds to either a complete image frame, or to a rectangular subsection thereof, referred to as a window. A first burst is defined to be a Header burst and contains an Image Header that specifies addresses of addressed workstations. Following the Header burst are image data bursts containing pixel data organized in raster format.

摘要翻译： 高速通信网络（10）提供单播，组播或广播图像数据能力，并且使用高性能并行接口（HPPI）作为物理信道来实现。 服务器（12）包括HPPI接收器和发射器。 工作站（18）支持HPPI兼容接收器（14b），但只需要一个简化的HPPI输出端口（20）。 这些工作站是连接的，每个的接收端口由数据和来自上游服务器HPPI发射器端口的控制信号驱动。 由接收器端口产生的握手信号，向服务器或上游工作站输出端口上行。 数据突发的分组对应于完整的图像帧，或对应于被称为窗口的矩形子部分。 第一个突发被定义为头部突发，并且包含一个指定寻址工作站的地址的图像头。 标题突发之后是包含以光栅格式组织的像素数据的图像数据突发。

公开(公告)号：US5420608A

公开(公告)日：1995-05-30

申请号：US187823

申请日：1994-01-27

申请人： Sung M. Choi ,  Leon Lumelsky ,  Alan W. Peevers ,  John L. Pittas

发明人： Sung M. Choi ,  Leon Lumelsky ,  Alan W. Peevers ,  John L. Pittas

IPC分类号： G06T9/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36 ,  H04N1/41 ,  G09G1/02

CPC分类号： G09G5/02

摘要： A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules. The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.

摘要翻译： 描述了一种显示系统，其包括用于接收呈现至少一对编码颜色的压缩像素图像的存储器和定义像素图像的像素子集的哪些像素接收一种颜色的位MASK。 该系统包括多个存储器模块。 子集中的像素在存储器模块中交错。 提供发生器用于施加信号以使数据被并行地写入每个模块。 提供寄存器装置用于将呈现编码颜色的数据应用于模块。 控制装置响应于MASK位，用于控制发生器并行并且在单个存储器周期中将经编码的颜色数据写入通过MASK位位置值为颜色指定的子集的所有像素位置。

公开(公告)号：US5196924A

公开(公告)日：1993-03-23

申请号：US733576

申请日：1991-07-22

申请人： Leon Lumelsky ,  Calvin B. Swart ,  John L. Pittas ,  Sung M. Choi ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Calvin B. Swart ,  John L. Pittas ,  Sung M. Choi ,  Alan W. Peevers

IPC分类号： H04N5/202 ,  G06T5/00 ,  G09G1/28 ,  G09G5/04 ,  G09G5/39

CPC分类号： G09G5/04 ,  G09G1/285 ,  G09G5/39 ,  G09G2320/0276

摘要： An image display system includes an input to a source (10, 12, 14) of image pixel data wherein each pixel is expressed as an M-bit value within a non-linear range of values. A first LUT (16) is coupled to an output of the source for converting each M-bit pixel value to an N-bit value within a linear range of values. An image memory, or frame buffer (18), has an input coupled to an output of the first LUT for storing the N-bit pixel values. The system further includes a second LUT (20) coupled to an output of the frame buffer for converting N-bit pixel values output by the frame buffer to P-bit pixel values within a non-linear range of values. The converted values are subsequently applied to a display (24). In an exemplary embodiment, the first LUT stores gamma corrected pixel values and the second LUT stores inverse gamma corrected pixel values. Preferably the second LUT stores a plurality of sets of inverse gamma corrected pixel values. Also, the frame buffer stores, for each of the N-bit pixel values, a value that specifies a particular one of the plurality of sets of inverse gamma corrected pixel values for use in converting an associated one of the N-bit pixel values.

公开(公告)号：US4949169A

公开(公告)日：1990-08-14

申请号：US428251

申请日：1989-10-27

申请人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Sung M. Choi ,  Alan W. Peevers

IPC分类号： H04N7/12 ,  H04M11/00 ,  H04N7/14 ,  H04N11/04 ,  H04N21/2383 ,  H04N21/438

CPC分类号： H04N21/2383 ,  H04N11/04 ,  H04N21/4382 ,  H04N7/148

摘要： An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of digital data (COMVIDOUT) comprising separate luminance and chrominance fields, from a digital TV source associated with each display node which data represents a scaled video window, (2) the local system clock (SCLK), (3) vertical and horizontal communication sync signals (COMVSOUT and COMSHOUT), (4) luminance and chrominance clock enable signals (COMYOCE and COMCOCE) based on a scaling algorithm utilized in the transmitting video device to insure that both the proper pixels and the proper luminance and chrominance fields associated with these pixels are selected by the communications device for transmission. Further, the interface architecture at each display node provides for receiving during a "receive mode", (5) video input data pixels (COMVIDIN), (6) a video input data clock enable signal from the communications adapter (COMVINCE) which controls the storage of the received video data window in the local frame buffer, (7) horizontal and vertical video input sync signals from the communications adapter (COMHSIN and COMVSIN) for properly synchronizing the storing of the received video input data from the communications adapter into the frame buffer beginning ata predetermined address therein. The system utilizes, to a great extent, exisiting hardware in conventional video display device architectures and associated communications adapters such that a versatile generally applicable transmission system is achievable requiring a minimum of additional control hardware and software.

公开(公告)号：US5220312A

公开(公告)日：1993-06-15

申请号：US414967

申请日：1989-09-29

申请人： Leon Lumelsky ,  Alan W. Peevers ,  Sung M. Choi

发明人： Leon Lumelsky ,  Alan W. Peevers ,  Sung M. Choi

IPC分类号： G06F3/153 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/395

CPC分类号： G09G5/36 ,  G09G5/14 ,  G09G5/395 ,  G09G2340/125

摘要： A locking mechanism is incorporated in a high-resolution video display system including a monitor, a computer for providing controls signals to said display system and two frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer. The output lock utilizes an extra bit-plane in the video buffer which stores a predetermined lock pattern and utilizes the normal monitor output port of the buffer operating under control of standard frame buffer addressing circuitry in combination with straight-forward combinational logic to achieve the locking function. The input lock utilizes a small DRAM which stores the input lock pattern data and utilizes this data in conjunction with normal write operations in the video buffer to control circuitry to disable the write function in predetermined regions of the video buffer.

公开(公告)号：US5119082A

公开(公告)日：1992-06-02

申请号：US415012

申请日：1989-09-29

申请人： Leon Lumelsky ,  Sung Min Choi ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Sung Min Choi ,  Alan W. Peevers

IPC分类号： H04N5/66 ,  G06T3/40 ,  G09G5/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  H04N1/393 ,  H04N5/262 ,  H04N7/01

CPC分类号： G06T3/4023 ,  H04N5/2628

摘要： A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the control signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means.

摘要翻译： 提供了与高分辨率显示系统一起使用的视频像素呈现速率扩展电路。 整体显示系统包括高分辨率监视器，用于提供控制信号的计算机，包括用于存储计算机图形和电视视频图像的高分辨率帧缓冲器，并以由所述控制信号控制的速率读出所述视频数据，并提供所述 数据与高分辨率显示器进行显示。 本发明的扩展电路包括响应于由计算机生成的扩展模式的装置，用于改变从所述帧缓冲器读出的视频像素数据的时基。 电路包括响应于所述扩展模式的装置，用于选择性地重复所述视频显示器的预定扫描线，并且用于选择性地重复沿着给定扫描线的某些像素，以将从所述帧缓冲器读出的视频数据的时基与所述帧缓冲器读出的时基相匹配， 高分辨率显示器。 根据本发明的优选实施例，扩展电路用于修改以预定方式控制帧缓冲器的读出的控制信号，而无需任何附加的视频缓冲存储装置。

公开(公告)号：US5283561A

公开(公告)日：1994-02-01

申请号：US999182

申请日：1992-12-22

申请人： Leon Lumelsky ,  Daniel H. McCabe ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Daniel H. McCabe ,  Alan W. Peevers

IPC分类号： G09G5/14 ,  G09G5/391 ,  H04N9/64 ,  G09G1/06

CPC分类号： H04N9/641 ,  G09G5/14 ,  G09G5/391 ,  G09G2340/125

摘要： A circuit for interfacing between a digital-television circuit for producing pixel data for television images and a computer graphics display permits rapid scaling and positioning of live television images on the graphics display. In a preferred embodiment, the digital-television/computer-graphics interface circuit of the invention includes memory for storing a horizontal-scaling bit pattern and a vertical-scaling bit pattern. Such a preferred interface circuit is adapted to receive digital-television pixel data from the digital television circuit and, on a pixel-by-pixel basis depending on the state of corresponding bits in the horizontal-scaling bit pattern, to skip the pixel in the case of image contraction and to replicate the pixel in the case of image expansion. The preferred interface circuit is also adapted to receive digital-television pixel data on a television-line by television-line basis and, depending on the state of a corresponding bit of the vertical-scaling bit pattern, to skip the entire line of pixel data in the case of image contraction or to replicate the line in the case of image expansion. The interface circuit may include a hardware vector generator for generating scaling bit patterns in accordance with a procedure analogous to a vector-drawing procedure used in graphics displays, such as the "Bresenham procedure."

摘要翻译： 用于产生用于电视图像的像素数据的数字电视电路和计算机图形显示器之间的接口电路允许在图形显示器上快速缩放和定位直播电视图像。 在优选实施例中，本发明的数字电视/计算机 - 图形接口电路包括用于存储水平缩放位模式和垂直缩放位模式的存储器。 这种优选的接口电路适于从数字电视电路接收数字电视像素数据，并且在逐个像素的基础上，取决于水平缩放位模式中的相应位的状态来跳过 图像收缩的情况下，并且在图像扩展的情况下复制像素。 优选的接口电路还适于通过电视线接收电视线上的数字电视像素数据，并且根据垂直缩放位模式的相应比特的状态来跳过像素数据的整个行 在图像收缩的情况下或在图像扩展的情况下复制该行。 接口电路可以包括硬件向量生成器，用于根据类似于在诸如“Bresenham过程”的图形显示中使用的矢量绘制过程的过程产生缩放位模式。

公开(公告)号：US4994912A

公开(公告)日：1991-02-19

申请号：US314623

申请日：1989-02-23

申请人： Leon Lumelsky ,  Alan W. Peevers

发明人： Leon Lumelsky ,  Alan W. Peevers

IPC分类号： G06F3/16 ,  G06F3/048 ,  G06F3/14 ,  G09G5/00 ,  G09G5/12 ,  G09G5/397 ,  G09G5/399

CPC分类号： G09G5/397 ,  G09G2340/125 ,  G09G2360/126

摘要： A method and apparatus for synchronizing two independent rasters, such that a standard TV video and a high resolution computer generated graphics video may each be displayed on a high resolution graphics monitor. This is accomplished utilizing dual frame buffers. A TV frame buffer, comprises a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resolution graphics monitor. A high resolution frame buffer in a computer is utilized to store high resolution graphics which is read out synchronously with the high resolution graphics monitor. A switching mechanism selects which of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion. The computer provides computer data, including high resolution graphics data and audio data to the TV frame buffer, with the graphics data being stored in the on screen portion and the audio data being stored in the off screen portion. The audio data is read out to an audio circuit for replay. The graphics data is combined with the TV video for purposes of windowing.

公开(公告)号：US5261049A

公开(公告)日：1993-11-09

申请号：US733906

申请日：1991-07-22

申请人： Leon Lumelsky ,  Sung M. Choi

发明人： Leon Lumelsky ,  Sung M. Choi

IPC分类号： G06F12/06 ,  G06T1/60 ,  G06T9/00 ,  G09G5/00 ,  G09G5/02 ,  G09G5/36 ,  G09G5/393 ,  G09G5/395 ,  H04N1/64 ,  H04N5/907 ,  H04N9/804 ,  H04N9/808 ,  G06F15/20

CPC分类号： H04N1/64 ,  G09G5/02 ,  G09G5/393 ,  G09G5/395 ,  G09G2360/123 ,  H04N19/13 ,  H04N19/60 ,  H04N19/91

摘要： An image buffer semiconductor chip is described that includes circuitry for decompressing, compressed pixel image data such data comprising at least a pair of color codes and a bit mask including bit positions with values that define which pixels in a pixel subset of the pixel image receive the encoded color code data. The chip comprises a matrix of memory modules with the pixels in a pixel subset stored in an interleaved fashion, one pixel per module. A data bus communicates with all of the memory modules and broadcasts the color codes. A mask register stores the bit mask when it appears on the data bus. Circuitry selectively writes a first color code in the modules in accordance with bit values of a first kind in the MASK and writes the second color code into the modules in accordance with bit values of a second kind in the MASK.