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    MULTI-STANDARD, AUTOMATIC IMPEDANCE CONTROLLED DRIVER WITH SUPPLY REGULATION
    1.
    发明申请
    MULTI-STANDARD, AUTOMATIC IMPEDANCE CONTROLLED DRIVER WITH SUPPLY REGULATION 有权
    多标准，自动阻抗控制驱动器供电调节

    公开(公告)号：US20140035549A1

    公开(公告)日：2014-02-06

    申请号：US13564150

    申请日：2012-08-01

    申请人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

    发明人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

    IPC分类号： G05F3/08

    CPC分类号： G05F3/08 ,  H03F2200/03 ,  H04L25/0278 ,  H04L25/028

    摘要： A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

    摘要翻译： 预驱动器电路基于摆动指令，驱动器阻抗特性和输入信号产生驱动器偏置信号。 驱动器接收驱动器偏置信号，并作为响应产生具有摆幅并具有对应于偏置信号的输出阻抗的驱动器信号。 可选地，根据摆动，驾驶员从多个供应轨道中的可切换的一个接收功率。 可选地，驱动器具有电压控制的电阻元件，并且基于摆动命令和驱动器电压控制的电阻器元件的副本产生驱动器偏置信号。

    High speed data testing without high speed bit clock
    3.
    发明授权
    High speed data testing without high speed bit clock 有权
    无高速位时钟的高速数据测试

    公开(公告)号：US08630821B2

    公开(公告)日：2014-01-14

    申请号：US13189926

    申请日：2011-07-25

    申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    IPC分类号： G06F11/30

    CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

    AUTOMATIC DETECTION AND COMPENSATION OF FREQUENCY OFFSET IN POINT-TO-POINT COMMUNICATION
    4.
    发明申请
    AUTOMATIC DETECTION AND COMPENSATION OF FREQUENCY OFFSET IN POINT-TO-POINT COMMUNICATION 有权
    点对点通信中频率偏移的自动检测和补偿

    公开(公告)号：US20130216014A1

    公开(公告)日：2013-08-22

    申请号：US13401020

    申请日：2012-02-21

    申请人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang

    发明人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang

    IPC分类号： H03D3/24

    CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/081 ,  H04L7/0025 ,  H04L7/033

    摘要： Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.

    摘要翻译： 自动检测和补偿点对点通信中频偏的系统和方法。 突发模式时钟和数据恢复（CDR）系统包括以第一频率接收的输入数据和以第二频率工作的参考时钟。 包括第一门控压控振荡器（GVCO）的主锁相环（PLL）被配置为对准参考时钟和输入数据的相位，并提供相位误差信息和恢复的时钟。 第二个GVCO由恢复的时钟控制，以对输入数据进行采样。 包括从第二GVCO到主PLL的反馈路径的频率对准环路被配置为使用相位误差信息来校正第一频率和第二频率之间的频率偏移。

    SYSTEM AND METHOD OF CALIBRATING A PHASE-LOCKED LOOP WHILE MAINTAINING LOCK
    5.
    发明申请
    SYSTEM AND METHOD OF CALIBRATING A PHASE-LOCKED LOOP WHILE MAINTAINING LOCK 失效
    在保持锁定时校准相位锁定环的系统和方法

    公开(公告)号：US20130120072A1

    公开(公告)日：2013-05-16

    申请号：US13296389

    申请日：2011-11-15

    申请人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

    发明人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

    IPC分类号： H03L7/095 ,  G06F17/50

    CPC分类号： H03L7/0891

    摘要： A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

    摘要翻译： 在保持锁定的同时校准锁相环（PLL）的方法包括在PLL锁定到输入信号的同时检测到PLL中的振荡器的控制信号已经超过阈值。 作为响应，调整振荡器的工作电流以将控制信号返回低于阈值，同时保持锁定到输入信号。 调整工作电流包括缓慢地改变耦合到PLL的校准电路的输出电流，使PLL能够在调节工作电流期间保持对输入信号的锁定。

    METHOD, SYSTEM, AND CIRCUIT WITH A DRIVER OUTPUT INTERFACE HAVING A COMMON MODE CONNECTION COUPLED TO A TRANSISTOR BULK CONNECTION
    6.
    发明申请
    METHOD, SYSTEM, AND CIRCUIT WITH A DRIVER OUTPUT INTERFACE HAVING A COMMON MODE CONNECTION COUPLED TO A TRANSISTOR BULK CONNECTION 有权
    具有连接到晶体管大容量连接的共模连接的驱动器输出接口的方法，系统和电路

    公开(公告)号：US20130120028A1

    公开(公告)日：2013-05-16

    申请号：US13294928

    申请日：2011-11-11

    申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang

    发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang

    IPC分类号： H03K3/00 ,  G06F19/00

    CPC分类号： H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45085 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726

    摘要： A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

    摘要翻译： 具有共模连接的多端子输出包括具有第一端子和第二端子的输出端，并且在第一端子和第二端子之间具有共模连接。 晶体管的体连接耦合到共模连接。 产生第一组控制信号和第二组控制信号。 第一组控制信号中的每一个具有与第一功率域相关联的第一导轨电压电平。 第二组控制信号是从第一组控制信号产生的。 第二组控制信号中的每一个具有与第二功率域相关联的第二轨电压电平。 第二功率域与输出驱动器的输出的共模电压相关联。

    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK
    7.
    发明申请
    HIGH SPEED DATA TESTING WITHOUT HIGH SPEED BIT CLOCK 有权
    高速数据测试无高速位时钟

    公开(公告)号：US20130030767A1

    公开(公告)日：2013-01-31

    申请号：US13189926

    申请日：2011-07-25

    申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

    IPC分类号： G06F11/30

    CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

    摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

    摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

    Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection
    8.
    发明申请
    Method and Digital Circuit for Recovering a Clock and Data from an Input Signal Using a Digital Frequency Detection 有权
    使用数字频率检测从输入信号中恢复时钟和数据的方法和数字电路

    公开(公告)号：US20120109356A1

    公开(公告)日：2012-05-03

    申请号：US12938405

    申请日：2010-11-03

    申请人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang ,  Tirdad Sowlati

    发明人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang ,  Tirdad Sowlati

    IPC分类号： G01R13/02 ,  G06F19/00 ,  H03L7/06

    CPC分类号： H04L7/033 ,  H04L7/0337

    摘要： In a particular embodiment, a digital circuit includes a frequency detection circuit operative to compare information related to transitions between sequential samples of a received signal. The frequency detection circuit is further operative to generate a control signal to reduce a sampling rate of the received signal in response to a predetermined number of the sequential samples having a same value. The digital circuit also includes a digital phase detector operative to provide the information related to the transitions between sequential samples to the frequency detection circuit.

    摘要翻译： 在特定实施例中，数字电路包括频率检测电路，其可操作以比较与接收信号的连续采样之间的转换有关的信息。 频率检测电路进一步操作以产生控制信号，以响应于具有相同值的预定数量的顺序样本来减小接收信号的采样率。 该数字电路还包括一个数字相位检测器，可操作以提供与频率检测电路的连续样本之间的转换有关的信息。

    System and method of calibrating a phase-locked loop while maintaining lock
    10.
    发明授权
    System and method of calibrating a phase-locked loop while maintaining lock 失效
    同时保持锁定校准锁相环的系统和方法

    公开(公告)号：US08638173B2

    公开(公告)日：2014-01-28

    申请号：US13296389

    申请日：2011-11-15

    申请人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

    发明人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0891

    摘要： A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

    摘要翻译： 在保持锁定的同时校准锁相环（PLL）的方法包括在PLL锁定到输入信号的同时检测到PLL中的振荡器的控制信号已经超过阈值。 作为响应，调整振荡器的工作电流以将控制信号返回低于阈值，同时保持锁定到输入信号。 调整工作电流包括缓慢地改变耦合到PLL的校准电路的输出电流，使PLL能够在调节工作电流期间保持对输入信号的锁定。