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    Vertical Cross-Point Memory Arrays
    3.
    发明申请
    Vertical Cross-Point Memory Arrays 有权
    垂直交叉点记忆阵列

    公开(公告)号：US20130210211A1

    公开(公告)日：2013-08-15

    申请号：US13586094

    申请日：2012-08-15

    申请人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    发明人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    IPC分类号： H01L45/00

    CPC分类号： H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

    摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    摘要翻译： 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的一对水平线之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。

    Vertical cross-point memory arrays
    5.
    发明授权
    Vertical cross-point memory arrays 有权
    垂直交叉点存储器阵列

    公开(公告)号：US09419217B2

    公开(公告)日：2016-08-16

    申请号：US13586094

    申请日：2012-08-15

    申请人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    发明人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    IPC分类号： H01L21/20 ,  H01L45/00 ,  H01L27/24

    CPC分类号： H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

    摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    摘要翻译： 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的水平线对之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。