公开(公告)号：US08031099B2

公开(公告)日：2011-10-04

申请号：US12645488

申请日：2009-12-23

申请人： Lijie Zhao ,  Qinghua Yue ,  Gao Song

发明人： Lijie Zhao ,  Qinghua Yue ,  Gao Song

IPC分类号： H03M1/66

CPC分类号： H03M1/1033 ,  H03M1/468 ,  H03M1/68

摘要： A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

摘要翻译： 数模转换器（DAC）电路包括通常耦合到LSB节点的电容器的最低有效位（LSB）集合以及耦合到MSB节点的最高有效位（MSB）组的电容器。 段耦合电容耦合LSB和MSB节点。 LSB节点呈现寄生电容，这倾向于引入跳变误差电压。 数字输入信号施加到LSB和MSB电容，作为响应，在MSB节点上开发出模拟输出信号。 耦合到MSB节点的补偿电容器具有选择的补偿电容以抵消由寄生电容引入的跳跃误差电压。 当所有LSB电容器耦合到具有逻辑“0”状态的数字输入信号时，补偿电容器被使能。 否则，补偿电容器被禁用（例如，保持在浮置状态）。

公开(公告)号：US20110148675A1

公开(公告)日：2011-06-23

申请号：US12645488

申请日：2009-12-23

申请人： Lijie Zhao ,  Qinghua Yue ,  Gao Song

发明人： Lijie Zhao ,  Qinghua Yue ,  Gao Song

IPC分类号： H03M1/06

CPC分类号： H03M1/1033 ,  H03M1/468 ,  H03M1/68

摘要： A digital-to-analog converter (DAC) circuit includes a least significant bit (LSB) set of capacitors, each commonly coupled to an LSB node, and a most significant bit (MSB) set of capacitors, each coupled to an MSB node. A section-coupling capacitor couples the LSB and MSB nodes. The LSB node exhibits a parasitic capacitance, which tends to introduce a jump error voltage. Digital input signals are applied to the LSB and MSB capacitors, and in response, an analog output signal is developed on the MSB node. A compensation capacitor coupled to the MSB node has a compensation capacitance selected to offset the jump error voltage introduced by the parasitic capacitance. The compensation capacitor is enabled when all of the LSB capacitors are coupled to digital input signals having a logic ‘0’ state. Otherwise, the compensation capacitor is disabled (e.g., left in a floating state).

摘要翻译： 数模转换器（DAC）电路包括通常耦合到LSB节点的电容器的最低有效位（LSB）集合以及耦合到MSB节点的最高有效位（MSB）组的电容器。 段耦合电容耦合LSB和MSB节点。 LSB节点呈现寄生电容，这倾向于引入跳变误差电压。 数字输入信号施加到LSB和MSB电容，作为响应，在MSB节点上开发出模拟输出信号。 耦合到MSB节点的补偿电容器具有选择的补偿电容以抵消由寄生电容引入的跳跃误差电压。 当所有LSB电容器耦合到具有逻辑“0”状态的数字输入信号时，补偿电容器被使能。 否则，补偿电容器被禁用（例如，保持在浮置状态）。

公开(公告)号：US20100309035A1

公开(公告)日：2010-12-09

申请号：US12481423

申请日：2009-06-09

申请人： QINGHUA YUE ,  Lijie Zhao ,  Song Gao

发明人： QINGHUA YUE ,  Lijie Zhao ,  Song Gao

IPC分类号： H03M1/02

CPC分类号： H03M1/0845 ,  H03M1/466 ,  H03M1/804

摘要： A method and apparatus for converting an analog input voltage signal to a discrete signal, the method including generating at least one reference voltage and at least one secondary voltage. The method further including selecting at least one voltage between the at least one reference voltage and the at least one secondary voltage and generating at least one intermediate voltage based on the at least one voltage and at least one digital code. The at least one intermediate voltage and the analog input voltage further being used to generate at least one comparison signal and the discrete signal being generated based on the at least one comparison signal and the at least one digital code.

摘要翻译： 一种用于将模拟输入电压信号转换为离散信号的方法和装置，所述方法包括生成至少一个参考电压和至少一个次级电压。 该方法还包括在所述至少一个参考电压和所述至少一个次级电压之间选择至少一个电压，并且基于所述至少一个电压和至少一个数字码产生至少一个中间电压。 所述至少一个中间电压和所述模拟输入电压进一步用于产生至少一个比较信号，并且所述离散信号是基于所述至少一个比较信号和所述至少一个数字码产生的。

公开(公告)号：US08378864B2

公开(公告)日：2013-02-19

申请号：US13049728

申请日：2011-03-16

申请人： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

发明人： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

IPC分类号： H03M1/06

CPC分类号： H03M1/06 ,  H03M1/468

摘要： Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

摘要翻译： 逐次近似公开了模数转换器（ADC）及相关方法。 逐次逼近ADC包括具有比较器输出的比较器和耦合到公共模型信号和比较输入的输入。 控制逻辑产生响应于比较器输出的一个或多个控制信号。 电容器阵列包括可操作地耦合到阵列输出的电容器的第一侧。 电容器阵列响应于一个或多个控制信号选择性地将电容器的第二侧的每一个耦合到模拟输入信号和一个或多个输入参考信号。 电压限制器可操作地耦合在阵列输出和比较器的比较输入之间，并将比较输入端的电压限制在相对于阵列输出的预定范围内。 逐次逼近ADC也可以与第二比较器和第二限压器差分地配置。

公开(公告)号：US08357244B1

公开(公告)日：2013-01-22

申请号：US12871747

申请日：2010-08-30

申请人： Lijie Zhao ,  Wei Zhang ,  Hongping Yuan

发明人： Lijie Zhao ,  Wei Zhang ,  Hongping Yuan

IPC分类号： B08B3/10

CPC分类号： G03F7/42 ,  G03F7/425 ,  H01L21/0272

摘要： A method of removing photoresist beneath an overlayer includes estimating a rapid temperature change for a photoresist layer to produce cracking in the overlayer. The temperature chance is estimated so that the cracking of the overlayer is sufficient to allow a liftoff solution to penetrate below the overlayer during a liftoff step. The method further includes baking the photoresist layer and chilling the photoresist layer after baking to produce the rapid temperature change. The method then includes lifting off the photoresist layer using the liftoff solution.

摘要翻译： 在覆盖层之下去除光致抗蚀剂的方法包括估计光致抗蚀剂层的快速温度变化以在覆盖层中产生裂纹。 估计温度机会，使得覆盖层的裂纹足以允许提升溶液在脱模步骤期间穿透覆盖层下方。 该方法还包括烘烤光致抗蚀剂层并且在烘烤之后使光致抗蚀剂层冷却以产生快速的温度变化。 该方法然后包括使用提升溶液提起光致抗蚀剂层。

公开(公告)号：US20120235846A1

公开(公告)日：2012-09-20

申请号：US13049728

申请日：2011-03-16

申请人： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

发明人： Lijie Zhao ,  Song Gao ,  Quinghua Hubert Yue ,  Jeffrey G. Barrow

IPC分类号： H03M1/34

CPC分类号： H03M1/06 ,  H03M1/468

摘要： Successive approximation Analog-to-digital converters (ADCs) and related methods are disclosed. A successive approximation ADC includes a comparator with a comparator output and inputs coupled to a common model signal and a compare input. Control logic generates one or more control signals responsive to the comparator output. A capacitor array includes first sides of capacitors operably coupled to an array output. The capacitor arrays selectively couples each of second sides of the capacitors to an analog input signal and one or more input reference signals responsive to the one or more control signals. A voltage limiter is operably coupled between the array output and the compare input of the comparator and limits a voltage on the compare input to within a predefined range relative to the array output. The successive approximation ADC may also be configured differentially with a second comparator and a second voltage limiter.

摘要翻译： 逐次近似公开了模数转换器（ADC）及相关方法。 逐次逼近ADC包括具有比较器输出的比较器和耦合到公共模型信号和比较输入的输入。 控制逻辑产生响应于比较器输出的一个或多个控制信号。 电容器阵列包括可操作地耦合到阵列输出的电容器的第一侧。 电容器阵列响应于一个或多个控制信号选择性地将电容器的第二侧的每一个耦合到模拟输入信号和一个或多个输入参考信号。 电压限制器可操作地耦合在阵列输出和比较器的比较输入之间，并将比较输入端的电压限制在相对于阵列输出的预定范围内。 逐次逼近ADC也可以与第二比较器和第二限压器差分地配置。

公开(公告)号：US08308921B1

公开(公告)日：2012-11-13

申请号：US11643494

申请日：2006-12-21

申请人： Hugh C. Hiner ,  Lijie Zhao ,  Hariharakeshava Hegde

发明人： Hugh C. Hiner ,  Lijie Zhao ,  Hariharakeshava Hegde

IPC分类号： C23C14/00

CPC分类号： C23C14/042 ,  C23C14/221 ,  H01J2237/3146

摘要： A shaper mask for particle flux includes a central portion extending from a body of the shaper mask along a first axis to block at least a first portion of a particle flux through the shaper mask from a first direction. The mask also includes at least one off-axis portion. Each off-axis portions extends from the body of the shaper mask along a respective second axis different from the first axis. Each off-axis portion is shaped to block a respective second portion of the particle flux traveling through the shaper mask from a second direction different from the first direction.

摘要翻译： 用于颗粒通量的成形器掩模包括从成形器罩体的主体沿着第一轴延伸的中心部分，以从第一方向阻挡通过整形罩的颗粒通量的至少第一部分。 掩模还包括至少一个离轴部分。 每个离轴部分沿着不同于第一轴线的相应第二轴线从整形器掩模的主体延伸。 每个离轴部分被成形为从不同于第一方向的第二方向阻挡穿过整形罩的颗粒通量的相应第二部分。

公开(公告)号：US08846534B1

公开(公告)日：2014-09-30

申请号：US13269453

申请日：2011-10-07

申请人： Yunfei Li ,  Ge Yi ,  Dujiang Wan ,  Guanghong Luo ,  Lijie Zhao ,  Yanfeng Chen ,  Lily Yao ,  Ming Jiang

发明人： Yunfei Li ,  Ge Yi ,  Dujiang Wan ,  Guanghong Luo ,  Lijie Zhao ,  Yanfeng Chen ,  Lily Yao ,  Ming Jiang

IPC分类号： H01L21/302

CPC分类号： G11B5/3163

摘要： Embodiments of the present invention relate to reducing the size variation on a wafer fabrication. In some embodiments, at least a portion the backfill material over features larger than a threshold size is etched or milled to provide backfill protrusions over those features. The backfill protrusions are configured to reduce the size variation across the fabrication. Embodiments of the invention may be used in fabrication of many types of devices, such as tapered wave guides (TWG), near-field transducers (NFT), MEMS devices, EAMR optical devices, optical structures, bio-optical devices, micro-fluidic devices, and magnetic writers.

摘要翻译： 本发明的实施例涉及减小晶片制造的尺寸变化。 在一些实施例中，至少一部分覆盖材料超过阈值尺寸的特征被蚀刻或研磨以在这些特征上提供回填突起。 回填突起构造成减小制造过程中的尺寸变化。 本发明的实施例可用于制造诸如锥形波导（TWG），近场换能器（NFT），MEMS装置，EAMR光学装置，光学结构，生物光学装置，微流体 设备和磁性作者。

公开(公告)号：US08163185B1

公开(公告)日：2012-04-24

申请号：US12059903

申请日：2008-03-31

申请人： Hai Sun ,  Liubo Hong ,  Rowena Schmidt ,  Lijie Zhao ,  Winnie Yu ,  Hongping Yuan

发明人： Hai Sun ,  Liubo Hong ,  Rowena Schmidt ,  Lijie Zhao ,  Winnie Yu ,  Hongping Yuan

IPC分类号： B44C1/22

CPC分类号： G11B5/3163 ,  Y10T29/49032

摘要： A method of lifting off photoresist beneath an overlayer includes providing a structure including photoresist and depositing an overlayer impenetrable to a liftoff solution over the photoresist and a field region around the structure. The method also includes forming a mask over the structure and ion milling to remove the overlayer in the field region not covered by the mask. The method then includes lifting off the photoresist using the liftoff solution.

摘要翻译： 提供覆盖层下面的光致抗蚀剂的方法包括提供包括光致抗蚀剂的结构，以及沉积在光致抗蚀剂上的不透气的覆盖层和围绕结构的场区域的覆盖层。 该方法还包括在结构上形成掩模和离子研磨以去除未被掩模覆盖的场区域中的覆盖层。 该方法然后包括使用提升溶液提取光致抗蚀剂。