公开(公告)号：US08841962B1

公开(公告)日：2014-09-23

申请号：US13871981

申请日：2013-04-26

Applicant: Linear Technology Corporation

Inventor： Gerd Trampitsch

IPC: H03K5/00 ,  H03F1/34

CPC classification number: H03F3/45475 ,  H03F2203/45514

Abstract: Methods and systems for a differential correlated double sampling (CDS) switched capacitor integrator circuit. The circuit includes a differential amplifier that has a differential input and a differential output. There is a first feedback path between the negative output node and the positive input node, and a second feedback path between the positive output node and the negative input node. Each feedback path includes an integration capacitor and at least one switch that has a parasitic capacitance. A first capacitive element is coupled between the negative input node and the negative output node, and a second capacitive element is coupled between the positive input node and the positive output node. Each capacitive element is configured to cancel the parasitic capacitance of its corresponding feedback path.

Abstract translation: 差分相关双采样（CDS）开关电容积分电路的方法和系统。 该电路包括具有差分输入和差分输出的差分放大器。 在负输出节点和正输入节点之间存在第一反馈路径，以及在正输出节点和负输入节点之间的第二反馈路径。 每个反馈路径包括积分电容器和至少一个具有寄生电容的开关。 第一电容元件耦合在负输入节点和负输出节点之间，第二电容元件耦合在正输入节点和正输出节点之间。 每个电容元件被配置为抵消其对应的反馈路径的寄生电容。

公开(公告)号：US08907703B1

公开(公告)日：2014-12-09

申请号：US13841459

申请日：2013-03-15

Applicant: Linear Technology Corporation

Inventor： Gerd Trampitsch

IPC: G11C27/02 ,  H03K5/00 ,  H03K17/00

CPC classification number: G11C27/024 ,  H03M1/1245

Abstract: Methods and systems for sampling a differential signal. The sampling circuit includes a differential input and a differential output. A logic control block, which is powered by VDD and VSS sources, controls the state of switches used to sample and store differential signals. The logic control block is AC coupled to the switches. The sampling circuit is configured to sample a common mode voltage at the differential input of a level that exceeds that of the VDD and VSS sources.

Abstract translation: 用于采样差分信号的方法和系统。 采样电路包括差分输入和差分输出。 由VDD和VSS源供电的逻辑控制块控制用于采样和存储差分信号的开关状态。 逻辑控制块与交换机交流耦合。 采样电路被配置为在差分输入端采样超过VDD和VSS源的电平的共模电压。

公开(公告)号：US09571052B1

公开(公告)日：2017-02-14

申请号：US14336653

申请日：2014-07-21

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Gerd Trampitsch

IPC: H03F3/45 ,  H03G3/04 ,  H03G3/00

CPC classification number: H03G1/0023 ,  H03F3/45188 ,  H03F3/45677 ,  H03F2200/129 ,  H03F2203/45008 ,  H03F2203/45288 ,  H03F2203/45336 ,  H03F2203/45528 ,  H03G1/0029

Abstract: A circuit may increase input transconductance. An input stage may include a field effect transistor (FET) that has a gate, source, drain, and body terminal. An amplifier may generate an amplified version of the input voltage received that is applied to the body terminal of the FET. Application of the amplified version to the body terminal of the FET may increase the transconductance of the FET compared to what it would be in the same circuit without the amplified version being applied to the body terminal of the FET.

Abstract translation: 电路可能会增加输入跨导。 输入级可以包括具有栅极，源极，漏极和主体端子的场效应晶体管（FET）。 放大器可以产生被施加到FET的体式端子的接收的输入电压的放大版本。 将放大版本应用到FET的体电极端子可以增加FET的跨导，而不会将放大版本施加到FET的体电极端子，而不会在同一电路中。

公开(公告)号：US09172364B2

公开(公告)日：2015-10-27

申请号：US14157300

申请日：2014-01-16

Applicant: Linear Technology Corporation

Inventor： Gerd Trampitsch

IPC: H03M1/12 ,  H03K17/06 ,  H03K17/16 ,  H03K3/356

CPC classification number: H03K17/063 ,  G11C27/02 ,  H03K3/356034 ,  H03K17/165 ,  H03K2217/0009 ,  H03K2217/0054 ,  H03M1/124 ,  H03M1/129

Abstract: A bootstrapped switch circuit capable of operating at input signals from far below the negative supply rail to far beyond the positive supply rail may include (a) a switch having a first terminal coupled to an input terminal, a second terminal coupled to an output terminal, and a control terminal; (b) a charge pump coupled to one or more clock signals and isolated from a timing circuit via a first capacitor and a second capacitor, the charge pump generating an output voltage; and (c) a logic circuit coupled to one or more clock signals and isolated from the timing control circuit via a third capacitor and a fourth capacitor, wherein the logic circuit provides a control signal to the control terminal of the switch that is derived from the output voltage of the charge pump.

Abstract translation: 能够在远离正电源轨的输入信号下工作的自举开关电路可以包括（a）具有耦合到输入端的第一端子，耦合到输出端子的第二端子的开关， 和控制终端; （b）电荷泵，其耦合到一个或多个时钟信号，并经由第一电容器和第二电容器与定时电路隔离，所述电荷泵产生输出电压; 以及（c）逻辑电路，其耦合到一个或多个时钟信号，并经由第三电容器和第四电容器与所述定时控制电路隔离，其中所述逻辑电路向所述开关的控制端提供控制信号， 电荷泵的输出电压。

公开(公告)号：US09077374B2

公开(公告)日：2015-07-07

申请号：US14052479

申请日：2013-10-11

Applicant: Linear Technology Corporation

Inventor： Gerd Trampitsch

IPC: H03M3/00 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M3/472 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1225 ,  H03M3/30 ,  H03M3/39 ,  H03M3/458 ,  H03M3/464

Abstract: A method and an ADC circuit use multiple SD modulations on an analog value and apply digital post-processing of the pulse density modulation (PDM) streams from the SD modulations obtaining a higher resolution in the digital output value for a given oversampling ratio. SD ADC does not face the constraint of conversion time doubling for each additional bit of resolution. In one implementation, an SD ADC includes conversions in SD phase and resolution-boosting phase. During SD phase, MSBs of the digital output value are generated from the sampled analog value using a first SD conversion. At the end of SD phase, the sampled analog value is reduced to “residual quantization error,” which remains in a capacitor of an integrator of SD ADC. In resolution-boosting phase, the LSBs of the digital output value are generated from residual quantization error using a second SD conversion that provides at least the LSBs.

Abstract translation: 方法和ADC电路对模拟值使用多个SD调制，并对来自SD调制的脉冲密度调制（PDM）流的数字后处理在给定的过采样比获得更高分辨率的数字输出值中。 SD ADC不会面临每个额外的分辨率的转换时间加倍的约束。 在一个实现中，SD ADC包括在SD相和分辨率提升阶段的转换。 在SD相位期间，使用第一次SD转换从采样的模拟值产生数字输出值的MSB。 在SD相结束时，采样的模拟值减少到残留在SD ADC积分器的电容器中的“残留量化误差”。 在分辨率提升阶段，使用提供至少LSB的第二SD转换，从残余量化误差产生数字输出值的LSB。

公开(公告)号：US08890577B1

公开(公告)日：2014-11-18

申请号：US14157316

申请日：2014-01-16

Applicant: Linear Technology Corporation

Inventor： Gerd Trampitsch

IPC: H03K5/00 ,  H03K17/00

CPC classification number: G11C27/02 ,  G11C27/024 ,  G11C27/026 ,  H03K5/2481 ,  H03M1/1245

Abstract: A method and a circuit achieve fully isolated sampling of bipolar differential voltage signals. The isolated sampling network is suitable for applications in which sampling signals far outside of the supply voltages are desired. A sampling network of the present invention may sample a differential signal between voltages −VDSMAX and VDSMAX, even with common mode voltages that exceed the supply voltage (e.g., an input stage of an ADC). The bipolar isolated input sampling network may include a polarity comparator and sampling switches that operate as rectifiers. Rectification ensures that a unipolar sampling network needs only to sample signals of predetermined voltage levels.

Abstract translation: 一种方法和电路实现了双极差分电压信号的完全隔离采样。 隔离采样网络适用于远远超出供电电压范围的采样信号的应用。 本发明的采样网络即使在超过电源电压的共模电压（例如，ADC的输入级）上也可以对电压-VDSMAX和VDSMAX之间的差分信号进行采样。 双极隔离输入采样网络可以包括作为整流器工作的极性比较器和采样开关。 整流确保单极采样网络仅需要采样预定电压电平的信号。