公开(公告)号：US06622907B2

公开(公告)日：2003-09-23

申请号：US10078948

申请日：2002-02-19

申请人： Lisa A. Fanti ,  Randolph F. Knarr ,  Erik J. Roggeman ,  Kamalesh K. Srivastava

发明人： Lisa A. Fanti ,  Randolph F. Knarr ,  Erik J. Roggeman ,  Kamalesh K. Srivastava

IPC分类号： B23K3102

CPC分类号： H01L24/05 ,  B23K35/001 ,  B23K35/007 ,  H01L21/2885 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11472 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00014

摘要： Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next. Form C4 solder bumps on the plating sites on the base/barrier layer within the C4 solder bump openings, with the C4 solder bumps being in contact with the conductive metal layer on the periphery of the through holes. Remove the mask. Etch away the remainder of the conductive metal layer, and etch away the base aside from the C4 solder bumps forming BLM pads. Then reflow the C4 solder bumps to form C4 solder balls.

摘要翻译： 从具有通过绝缘层暴露的触点的半导体衬底开始。 在触点上形成一个基底，底部由至少一个金属层组成。 然后在基底上形成导电金属层。 在导电金属层的顶表面上形成具有C4焊料凸块开口的掩模，其中C4焊料凸块图像的形状向下到触点上方的导电金属层的表面。 将C4导电金属层下方的导电金属层的露出部分刻蚀掉，以形成导电金属层中的通孔，露出C4焊料凸块开口下方的基座顶面上的C4焊料凸块电镀部位，导电金属层保留 在C4焊料凸点电镀部位的通孔的外围是完整的。 作为选择，接下来在电镀位置上形成阻挡层。 在C4焊料凸点开口内的基底/阻挡层上的电镀部位上形成C4焊料凸块，其中C4焊料凸块与通孔周边上的导电金属层接触。 取下面具。 蚀刻掉导电金属层的剩余部分，并且除了形成BLM焊盘的C4焊料凸块之外蚀刻掉基部。 然后回流C4焊锡凸块形成C4焊球。

公开(公告)号：US06992389B2

公开(公告)日：2006-01-31

申请号：US10709321

申请日：2004-04-28

申请人： Panayotis C. Andricacos ,  Tien-Jen J. Cheng ,  Emanuel I. Cooper ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Roger A. Quon ,  Erik J. Roggeman

发明人： Panayotis C. Andricacos ,  Tien-Jen J. Cheng ,  Emanuel I. Cooper ,  David E. Eichstadt ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Roger A. Quon ,  Erik J. Roggeman

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/60 ,  H01L23/485

CPC分类号： H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/00014

摘要： A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

摘要翻译： 创建用于在互连中使用的多层屏障的方法，用于互连的阻挡，以及包括该阻挡互连中公开。 该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。 所述屏障至少包括富镍材料制成的第一层和富铜材料制成的第二层。 该屏障允许使用用于高级互补金属氧化物半导体（CMOS）的设计更高的电流密度的，并延伸当前的CMOS的可靠性设计不管焊料选择。 此外，这种技术很容易适应制造电镀互连，如C4S的当前方法。