公开(公告)号：US20120168743A1

公开(公告)日：2012-07-05

申请号：US13097082

申请日：2011-04-29

申请人： Liu-Chung Lee ,  Hung-Che Ting ,  Chia-Yu Chen

发明人： Liu-Chung Lee ,  Hung-Che Ting ,  Chia-Yu Chen

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L29/78693

摘要： A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.

摘要翻译： 提供了包括栅极，栅极绝缘体，氧化物半导体沟道层，源极和漏极的薄膜晶体管（TFT）。 栅极绝缘体覆盖栅极，而氧化物半导体沟道层配置在栅极绝缘体上并位于栅极上方。 氧化物半导体沟道层包括位于第一子层上的第一子层和第二子层。 第一子层的氧含量低于第二子层的氧含量。 源极和漏极配置在第二子层的一部分上。 此外，还提供了上述TFT的制造方法。

公开(公告)号：US08647934B2

公开(公告)日：2014-02-11

申请号：US13097082

申请日：2011-04-29

申请人： Liu-Chung Lee ,  Hung-Che Ting ,  Chia-Yu Chen

发明人： Liu-Chung Lee ,  Hung-Che Ting ,  Chia-Yu Chen

IPC分类号： H01L21/84

CPC分类号： H01L29/7869 ,  H01L29/78693

摘要： A thin film transistor (TFT) including a gate, a gate insulator, an oxide semiconductor channel layer, a source, and a drain is provided. The gate insulator covers the gate, while the oxide semiconductor channel layer is configured on the gate insulator and located above the gate. The oxide semiconductor channel layer includes a first sub-layer and a second sub-layer located on the first sub-layer. An oxygen content of the first sub-layer is lower than an oxygen content of the second sub-layer. The source and the drain are configured on a portion of the second sub-layer. In addition, a fabricating method of the above-mentioned TFT is also provided.

摘要翻译： 提供了包括栅极，栅极绝缘体，氧化物半导体沟道层，源极和漏极的薄膜晶体管（TFT）。 栅极绝缘体覆盖栅极，而氧化物半导体沟道层配置在栅极绝缘体上并位于栅极上方。 氧化物半导体沟道层包括位于第一子层上的第一子层和第二子层。 第一子层的氧含量低于第二子层的氧含量。 源极和漏极配置在第二子层的一部分上。 此外，还提供了上述TFT的制造方法。

公开(公告)号：US07981708B1

公开(公告)日：2011-07-19

申请号：US12908872

申请日：2010-10-20

申请人： Liu-Chung Lee ,  Hung-Che Ting ,  Chia-Yu Chen

发明人： Liu-Chung Lee ,  Hung-Che Ting ,  Chia-Yu Chen

IPC分类号： H01L21/00

CPC分类号： H01L27/3248 ,  H01L27/1225 ,  H01L27/3262

摘要： A method of fabricating a pixel structure is provided. A gate electrode is formed on a substrate, and a dielectric layer is formed on the gate electrode. A patterned metal oxide semiconductor layer and a patterned metallic etching stop layer are formed on the dielectric layer above the gate electrode. A first conductive layer is formed to cover the patterned metallic etching stop layer and the dielectric layer. The first conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a source and a drain. A second conductive layer is formed to cover the source, the drain and the dielectric layer. The second conductive layer is patterned by using the patterned metallic etching stop layer as an etching stop layer to form a first electrode layer. The patterned metallic etching stop layer exposed between the source and the drain is removed.

摘要翻译： 提供了一种制造像素结构的方法。 在基板上形成栅电极，在栅电极上形成介电层。 在栅电极上的电介质层上形成图案化的金属氧化物半导体层和图案化的金属蚀刻停止层。 形成第一导电层以覆盖图案化的金属蚀刻停止层和电介质层。 通过使用图案化的金属蚀刻停止层作为蚀刻停止层来形成第一导电层以形成源极和漏极。 形成第二导电层以覆盖源极，漏极和介电层。 通过使用图案化的金属蚀刻停止层作为蚀刻停止层来图案化第二导电层，以形成第一电极层。 去除在源极和漏极之间暴露的图案化金属蚀刻停止层。

公开(公告)号：US08969146B2

公开(公告)日：2015-03-03

申请号：US13615661

申请日：2012-09-14

申请人： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

发明人： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC分类号： H01L21/84

CPC分类号： H01L27/1288 ,  H01L21/28008 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L2227/323

摘要： A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

摘要翻译： 阵列基板的制造方法包括以下步骤。 在基板上依次形成栅极电极和栅极绝缘体层。 在栅极绝缘体层上依次形成半导体层，蚀刻停止层，硬掩模层和第二图案化光致抗蚀剂。 第二图案化的光致抗蚀剂用于对硬掩模层进行过蚀刻工艺以形成图案化的硬掩模层。 第二图案化光刻胶用于对蚀刻停止层进行第一蚀刻处理。 然后使用第二图案化的光致抗蚀剂来对半导体层执行第二蚀刻工艺以形成图案化的半导体层。 由图案化的硬掩模层未覆盖的蚀刻停止层然后被去除以形成图案化的蚀刻停止层。

公开(公告)号：US20130134425A1

公开(公告)日：2013-05-30

申请号：US13615661

申请日：2012-09-14

申请人： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

发明人： Yi-Chen Chung ,  Chia-Yu Chen ,  Hui-Ling Ku ,  Yu-Hung Chen ,  Chi-Wei Chou ,  Fan-Wei Chang ,  Hsueh-Hsing Lu ,  Hung-Che Ting

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/15 ,  H01L33/08

CPC分类号： H01L27/1288 ,  H01L21/28008 ,  H01L21/31133 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L2227/323

摘要： A manufacturing method of an array substrate includes the following steps. A gate electrode and a gate insulator layer are successively formed on a substrate. A semiconductor layer, an etching stop layer, a hard mask layer, and a second patterned photoresist are successively formed on the gate insulator layer. The second patterned photoresist is employed for performing an over etching process to the hard mask layer to form a patterned hard mask layer. The second patterned photoresist is employed for performing a first etching process to the etching stop layer. The second patterned photoresist is then employed for performing a second etching process to the semiconductor layer to form a patterned semiconductor layer. The etching stop layer uncovered by the patterned hard mask layer is then removed for forming a patterned etching stop layer.

摘要翻译： 阵列基板的制造方法包括以下步骤。 在基板上依次形成栅极电极和栅极绝缘体层。 在栅极绝缘体层上依次形成半导体层，蚀刻停止层，硬掩模层和第二图案化光致抗蚀剂。 第二图案化的光致抗蚀剂用于对硬掩模层进行过蚀刻工艺以形成图案化的硬掩模层。 第二图案化光刻胶用于对蚀刻停止层进行第一蚀刻处理。 然后使用第二图案化的光致抗蚀剂来对半导体层执行第二蚀刻工艺以形成图案化的半导体层。 由图案化的硬掩模层未覆盖的蚀刻停止层然后被去除以形成图案化的蚀刻停止层。

公开(公告)号：US20110193089A1

公开(公告)日：2011-08-11

申请号：US12753098

申请日：2010-04-01

申请人： Cheng-Wei Chou ,  Hsueh-Hsing Lu ,  Hung-Che Ting ,  Tsung-Hsiang Shih ,  Chia-Yu Chen

发明人： Cheng-Wei Chou ,  Hsueh-Hsing Lu ,  Hung-Che Ting ,  Tsung-Hsiang Shih ,  Chia-Yu Chen

IPC分类号： H01L33/00 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A pixel structure including a substrate, a gate, an insulation layer, a metal oxide semiconductor (MOS) layer, a source and a drain, at least one film layer, and a first electrode layer is provided. The gate is disposed on the substrate. The insulation layer covers the gate. The MOS layer is disposed on the insulation layer above the gate. The source and the drain are disposed on the MOS layer. The film layer covers the MOS layer and includes a transparent photocatalytic material, wherein the transparent photocatalytic material blocks ultraviolet light from reaching the MOS layer. The first electrode layer is electrically connected to the source or the drain.

摘要翻译： 提供了包括基板，栅极，绝缘层，金属氧化物半导体（MOS）层，源极和漏极，至少一个膜层和第一电极层的像素结构。 栅极设置在基板上。 绝缘层覆盖门。 MOS层设置在栅极上方的绝缘层上。 源极和漏极设置在MOS层上。 膜层覆盖MOS层，并且包括透明光催化材料，其中透明光催化材料阻挡紫外光到达MOS层。 第一电极层电连接到源极或漏极。

公开(公告)号：US20070181421A1

公开(公告)日：2007-08-09

申请号：US11398684

申请日：2006-04-06

申请人： Hung-Wen Wei ,  Hung-Che Ting ,  Hsueh-Ying Chen

发明人： Hung-Wen Wei ,  Hung-Che Ting ,  Hsueh-Ying Chen

IPC分类号： C23C14/00

CPC分类号： C23C14/0047 ,  C23C14/354 ,  C23C14/358 ,  C23C14/562 ,  H01J37/32357 ,  H01J37/3408 ,  H01J37/3438

摘要： This invention provides a sputtering system providing large area sputtering and plasma-assisted reactive gas dissociation. A plurality of plasma sources is provided in a reaction chamber to dissociate at least one reactive gas. The dissociated reactive gas is doped in a film during the deposition of the film so as to control the composition of the film. The property of the film is thus improved. A composite film can be formed on the substrate by the present sputtering system. The present sputtering system is suitable for film deposition on a large-area hard substrate and flexible substrate.

摘要翻译： 本发明提供了一种提供大面积溅射和等离子体辅助反应气体解离的溅射系统。 在反应室中提供多个等离子体源以解离至少一个反应气体。 在膜的沉积期间，解离的反应气体被掺杂在膜中，以便控制膜的组成。 因此，电影的特性得到改善。 可以通过本溅射系统在基板上形成复合膜。 本溅射系统适用于大面积硬质基材和柔性基材上的薄膜沉积。

公开(公告)号：US20060148140A1

公开(公告)日：2006-07-06

申请号：US11252560

申请日：2005-10-19

申请人： Lin-En Chou ,  Hung-Che Ting

发明人： Lin-En Chou ,  Hung-Che Ting

IPC分类号： H01L21/84

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02274 ,  H01L21/02332 ,  H01L21/3143 ,  H01L21/3145 ,  H01L27/1214

摘要： A method for forming a silicon oxynitride layer, suitable to be used in the production of semiconductor devices, e.g. poly-silicon thin film transistors, is provided. A plasma surface treatment is performed over a substrate after a silicon nitride/silicon oxide layer has been formed on the substrate by a glow discharge system to transform the silicon nitride/silicon oxide layer into a silicon oxynitride layer. The semiconductor device may be completely manufactured in simplex equipment. Therefore, the production time and production cost are favorably reduced.

摘要翻译： 一种适用于制造半导体器件的氮氧化硅层的形成方法， 提供多晶硅薄膜晶体管。 在通过辉光放电系统在衬底上形成氮化硅/氧化硅层之后，在衬底上进行等离子体表面处理，以将氮化硅/氧化硅层转化为氮氧化硅层。 半导体器件可以在单工设备中完全制造。 因此，生产时间和生产成本有利地降低。

公开(公告)号：US08097083B2

公开(公告)日：2012-01-17

申请号：US11244040

申请日：2005-10-06

申请人： Hung-Wen Wei ,  Hung-Che Ting

发明人： Hung-Wen Wei ,  Hung-Che Ting

IPC分类号： C23C16/00

CPC分类号： C23C16/4412 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/45557 ,  C23C16/509 ,  C23C16/52

摘要： An operating method for a large dimension plasma enhanced atomic layer deposition cavity and an apparatus thereof are provided. The present invention reduces the time needed for filling the manufacturing gas into the large volume manufacturing cavity. Therefore, the plasma enhanced atomic layer deposition apparatus can switch the precursors rapidly to increase the thin film deposition rate, reduce the manufacturing gas consumption and lower the manufacturing cost.

摘要翻译： 提供了一种用于大尺寸等离子体增强原子层沉积腔的操作方法及其装置。 本发明减少了将制造气体填充到大体积制造腔中所需的时间。 因此，等离子体增强原子层沉积装置可以快速切换前体以增加薄膜沉积速率，降低制造气体消耗并降低制造成本。

公开(公告)号：US20070026162A1

公开(公告)日：2007-02-01

申请号：US11244040

申请日：2005-10-06

申请人： Hung-Wen Wei ,  Hung-Che Ting

发明人： Hung-Wen Wei ,  Hung-Che Ting

IPC分类号： H05H1/24 ,  C23C16/00

CPC分类号： C23C16/4412 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/45557 ,  C23C16/509 ,  C23C16/52

摘要： An operating method for a large dimension plasma enhanced atomic layer deposition cavity and an apparatus thereof are provided. The present invention reduces the time needed for filling the manufacturing gas into the large volume manufacturing cavity. Therefore, the plasma enhanced atomic layer deposition apparatus can switch the precursors rapidly to increase the thin film deposition rate, reduce the manufacturing gas consumption and lower the manufacturing cost.

摘要翻译： 提供了一种用于大尺寸等离子体增强原子层沉积腔的操作方法及其装置。 本发明减少了将制造气体填充到大体积制造腔中所需的时间。 因此，等离子体增强原子层沉积装置可以快速切换前体以增加薄膜沉积速率，降低制造气体消耗并降低制造成本。