-
公开(公告)号：US11977444B2
公开(公告)日：2024-05-07
申请号：US18200439
申请日：2023-05-22
CPC分类号： G06F11/1068 , G06F11/076 , G11C13/0026 , G11C13/0028 , G06F2201/88
摘要： An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
-
公开(公告)号：US20240126707A1
公开(公告)日：2024-04-18
申请号：US18373769
申请日：2023-09-27
IPC分类号： G06F13/16 , G06F3/06 , G06F13/40 , G11C7/22 , G11C11/406
CPC分类号： G06F13/1689 , G06F3/0604 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F13/4086 , G11C7/22 , G11C11/406
摘要： Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
-
公开(公告)号：US12056008B2
公开(公告)日：2024-08-06
申请号：US18195374
申请日：2023-05-10
IPC分类号： H03M13/09 , G06F11/10 , G11C11/406 , G11C11/408 , H04L1/00 , H04L45/7453 , H04L47/125
CPC分类号： G06F11/1068 , G11C11/406 , G11C11/4087
摘要： Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.
-
公开(公告)号：US20240203464A1
公开(公告)日：2024-06-20
申请号：US18513317
申请日：2023-11-17
IPC分类号： G11C7/10 , G06F11/30 , G11C11/4093
CPC分类号： G11C7/1045 , G06F11/3037 , G06F11/3058 , G11C7/1051 , G11C7/1078 , G11C11/4093
摘要： Memory devices, memory systems, and methods of operating the same are disclosed in which a memory device, in response to receiving a mode register read (MRR) command directed to one or more write-only bits of a mode register, reads data indicative of a status of the memory device about the memory device from one or more cells of a memory array of the memory device that are different from the write-only mode register. The data can include device settings, environmental conditions, usage statistics, metadata, feature support, feature implementation, device status, temperature, etc. The status information mode can be optionally enabled or disabled. The memory devices can include DDR5 DRAM memory devices.
-
公开(公告)号：US11775459B2
公开(公告)日：2023-10-03
申请号：US17712006
申请日：2022-04-01
CPC分类号： G06F13/1689 , G06F3/0604 , G06F3/0625 , G06F3/0659 , G06F3/0673 , G06F13/4086 , G11C7/22 , G11C11/406
摘要： Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
-
6.发明公开公开(公告)号：US20240289219A1
公开(公告)日：2024-08-29
申请号：US18652714
申请日：2024-05-01
CPC分类号： G06F11/1068 , G06F11/076 , G11C13/0026 , G11C13/0028 , G06F2201/88
摘要： An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
-
公开(公告)号：US20240127878A1
公开(公告)日：2024-04-18
申请号：US18384682
申请日：2023-10-27
IPC分类号： G11C11/406
CPC分类号： G11C11/40611 , G11C11/40618
摘要： Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
-
公开(公告)号：US11810610B2
公开(公告)日：2023-11-07
申请号：US17387934
申请日：2021-07-28
IPC分类号： G11C11/406
CPC分类号： G11C11/40611 , G11C11/40618
摘要： Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.013 秒)
