公开(公告)号：US20240422980A1

公开(公告)日：2024-12-19

申请号：US18818224

申请日：2024-08-28

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Xuan Li ,  Adeline Yii

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20240188288A1

公开(公告)日：2024-06-06

申请号：US18437665

申请日：2024-02-09

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H01L23/00 ,  H01L23/538 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76838 ,  H01L23/5386 ,  H01L24/14 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulative structures, first support pillar structures extending through the stack structure within a first region of the microelectronic device, the first support pillar structures electrically isolated from a source structure underlying the stack structure, second support pillar structures extending through the stack structure within a second region of the microelectronic device, the second support pillar structures comprising an electrically conductive material in electrical communication with the source structure, and bridge structures extending between at least some neighboring first support pillar structures of the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240147727A1

公开(公告)日：2024-05-02

申请号：US18400634

申请日：2023-12-29

Applicant: Lodestar Licensing Group LLC

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H10B43/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H10B41/41

CPC classification number: H10B43/40 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/535 ,  H10B41/41

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US12108600B2

公开(公告)日：2024-10-01

申请号：US18474061

申请日：2023-09-25

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Xuan Li ,  Adeline Yii

IPC: H01L21/00 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A microelectronic device comprises a stack structure, at least one staircase structure, contact structures, and support structures. The stack structure comprises vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures. The at least one staircase structure is within the stack structure and has steps comprising edges of at least some of the tiers. The contact structures are on the steps of the at least one staircase structure. The support structures horizontally alternate with the contact structures in a first horizontal direction and vertically extend through the stack structure. The support structures have oblong horizontal cross-sectional shapes. Additional microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20250024673A1

公开(公告)日：2025-01-16

申请号：US18896671

申请日：2024-09-25

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H10B41/27 ,  H01L21/768 ,  H01L23/532 ,  H10B43/27

Abstract: A microelectronic device comprising a stack structure comprising a non-staircase region, a staircase region, and an array region. Each of the non-staircase region, the staircase region, and the array region comprises tiers of alternating conductive materials and dielectric materials. One or more pillars are in the non-staircase region and in the array region, and one or more supports are in the staircase region. A conductive material is in each of the non-staircase region, the staircase region, and the array region and extends vertically into a source adjacent to the tiers. The source comprises corrosion containment features in each of the non-staircase region, the staircase region, and the array region, adjacent to the conductive material in the source. Additional microelectronic devices, electronic systems, and methods are also disclosed.

公开(公告)号：US20240136285A1

公开(公告)日：2024-04-25

申请号：US18400680

申请日：2023-12-29

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises pillar structures comprising semiconductive material, contact structures in physical contact with upper portions of the pillar structures, and conductive structures over and in physical contact with the contact structures. Each of the conductive structures comprises an upper portion having a first width, and a lower portion vertically interposed between the upper portion and the contact structures. The lower portion has a tapered profile defining additional widths varying from a second width less than the first width at an uppermost boundary of the lower portion to a third width less than the second width at a lowermost boundary of the lower portion. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11864380B2

公开(公告)日：2024-01-02

申请号：US17878574

申请日：2022-08-01

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo

IPC: H10B41/27 ,  G11C5/06 ,  G11C5/02 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a memory array region which includes channel material pillars extending through a stack of alternating conductive and insulative levels. A second region is adjacent the memory array region. A conductive expanse is within the memory array region and electrically coupled with the channel material of the channel material pillars. A panel extends across the memory array region and the second region. The panel separates one memory block region from another. The panel has a first portion over the conductive expanse, and has a second portion adjacent the first portion. The panel has a bottom surface. A first segment of the bottom surface is adjacent an upper surface of the conductive expanse. A segment of the bottom surface within the second portion is elevationally offset relative to the first segment. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12278180B2

公开(公告)日：2025-04-15

申请号：US17506821

申请日：2021-10-21

Applicant: Lodestar Licensing Group LLC

Inventor： Harsh Narendrakumar Jain ,  Shuangqiang Luo

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers having channel-material strings therein. Conductive vias are formed through insulating material that is directly above the channel-material strings. Individual of the conductive vias are directly electrically coupled to individual of the channel-material strings. After forming the conductive vias, horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Intervening material is formed in the trenches laterally-between and longitudinally-along the immediately-laterally-adjacent memory-block regions. Additional methods and structures independent of method are disclosed.

公开(公告)号：US20240138146A1

公开(公告)日：2024-04-25

申请号：US18382863

申请日：2023-10-22

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Justin B. Dorhout ,  Rita J. Klein

IPC: H10B41/41 ,  G11C5/06 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C5/063 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11937430B2

公开(公告)日：2024-03-19

申请号：US17841624

申请日：2022-06-15

Applicant: Lodestar Licensing Group LLC

Inventor： Shuangqiang Luo ,  Indra V. Chary

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first deck, a second deck over the first deck, and a third deck over the second deck. The first deck has first conductive levels disposed one atop another. The second deck has second conductive levels disposed one atop another. The third deck has third conductive levels disposed one atop another. A first staircase region extends to the first and second conductive levels, and passes through the third conductive levels. A second staircase region extends to the third conductive levels and not to the first and second conductive levels. Some embodiments include methods of forming integrated assemblies.