公开(公告)号：US06351429B1

公开(公告)日：2002-02-26

申请号：US09607097

申请日：2000-06-29

申请人： Louis L. Hsu ,  Dmitry Netis ,  John M. Ross

发明人： Louis L. Hsu ,  Dmitry Netis ,  John M. Ross

IPC分类号： G11C800

CPC分类号： G11C11/56 ,  G11C7/1006 ,  G11C8/10 ,  G11C16/08

摘要： An integrated circuit memory device comprising an arrangement of physical wordlines, WL0-WLn, arrange such that each wordline is addressed by a plurality of pairs, An+1, An, of logical row address bits, and such that at least one pair of logical row address bits, corresponding to physically adjacent wordlines Wlm, Wlm+1, Wlm+2 in succession, cycles between binary states which encode the ternary results A, B and C in succession. The ternary results A, B or C are used to determine which two bitlines of a possible three bitlines are selected by a multiplexer which connects the bitlines to a sense amplifier for determining the state of a bit stored in a memory cell accessed by an activated wordline and a selected bitline. Preferably, the ternary results A, B and C are respectively encoded by said binary states of said pair of logical row address bits, said binary states being “00,” “01,” and “10” respectively.

摘要翻译： 包括物理字线WL0-WLn的布置的集成电路存储器件被布置为使得每个字线由逻辑行地址位的多个对An + 1，An对寻址，并且使得至少一对逻辑 对应于物理上相邻的字线Wlm，Wlm + 1，Wlm + 2的行地址位，是连续编码三元结果A，B和C的二进制状态之间的循环。 三元结果A，B或C用于确定通过多路复用器选择可能的三个位线的两个位线，该多路复用器将位线连接到读出放大器，用于确定由激活的字线访问的存储器单元中存储的位的状态 和一个选定的位线。 优选地，三进制结果A，B和C分别由所述逻辑行地址位对的所述二进制状态分别编码，所述二进制状态分别为“00”，“01”和“10”。

公开(公告)号：US06551895B1

公开(公告)日：2003-04-22

申请号：US09666324

申请日：2000-09-21

申请人： Louis L. Hsu ,  Dmitry Netis

发明人： Louis L. Hsu ,  Dmitry Netis

IPC分类号： H01L2120

CPC分类号： H01L29/66181 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/94

摘要： A semiconductor structure (and method for manufacturing the same) comprises an active array of first elements having a first manufacturing precision, a peripheral region surrounding the active array, the peripheral region including second elements having a second manufacturing precision less than the first manufacturing precision, wherein the second elements are isolated from the active array and comprise passive devices for improving operations of the active array.

摘要翻译： 半导体结构（及其制造方法）包括具有第一制造精度的第一元件的有源阵列，围绕有源阵列的周边区域，所述周边区域包括具有小于第一制造精度的第二制造精度的第二元件， 其中所述第二元件与所述有源阵列隔离并且包括用于改善所述有源阵列的操作的无源器件。

公开(公告)号：US6157067A

公开(公告)日：2000-12-05

申请号：US224767

申请日：1999-01-04

申请人： Louis L. Hsu ,  Dmitry Netis

发明人： Louis L. Hsu ,  Dmitry Netis

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/062

CPC分类号： H01L29/66181 ,  H01L27/10897 ,  H01L29/94 ,  H01L27/10894

摘要： A semiconductor structure (and method for manufacturing the same) comprises an active array of first elements having a first manufacturing precision, a peripheral region surrounding the active array, the peripheral region including second elements having a second manufacturing precision less than the first manufacturing precision, wherein the second elements are isolated from the active array and comprise passive devices for improving operations of the active array.

公开(公告)号：US06477630B2

公开(公告)日：2002-11-05

申请号：US09257146

申请日：1999-02-24

申请人： Brian Ji ,  Toshiaki Kirihata ,  Dmitry Netis

发明人： Brian Ji ,  Toshiaki Kirihata ,  Dmitry Netis

IPC分类号： G06F1300

CPC分类号： G11C11/4097 ,  G11C11/4087

摘要： A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.

摘要翻译： 存储器结构包括多个存储体（每个存储体包括多个块）连接到相应存储体中的所有块的多个时序关键地址线（关键地址线的数量等于 银行数量）以及连接到各个块的多个专用地址线。

公开(公告)号：US06272062B1

公开(公告)日：2001-08-07

申请号：US09583596

申请日：2000-05-31

申请人： Gerhard Mueller ,  Toshiaki Kirihata ,  Dmitry Netis

发明人： Gerhard Mueller ,  Toshiaki Kirihata ,  Dmitry Netis

IPC分类号： G11C800

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097

摘要： There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.

摘要翻译： 提供一种半导体存储器件，其包括：以至少两组布置的多个存储单元; 至少一个读出放大器; 第一和第二多路复用器; 和至少一个可编程控制装置。 每个多路复用器适于将至少一个组耦合到放大器。 可编程控制装置适于控制第一和第二多路复用器。 在一个实施例中，可编程控制装置适于独立地控制多路复用器。

公开(公告)号：US06236258B1

公开(公告)日：2001-05-22

申请号：US09139514

申请日：1998-08-25

申请人： Heinz Hoenigschmid ,  Dmitry Netis

发明人： Heinz Hoenigschmid ,  Dmitry Netis

IPC分类号： H03K301

CPC分类号： H01L27/108 ,  H01L27/105

摘要： An arrangement of enhanced drivability transistors is disclosed herein which includes a plurality of conductor patterns, wherein the conductor patterns include ring-shaped portions which enclose device diffusion contacts and the ring-shaped portions form the gate conductors of insulated gate field effect transistors (IGFETs).

摘要翻译： 本文公开了一种增强驱动力晶体管的布置，其包括多个导体图案，其中导体图案包括环形部分，其环绕器件扩散接触，并且环形部分形成绝缘栅场效应晶体管（IGFET）的栅极导体， 。