公开(公告)号：US06272062B1

公开(公告)日：2001-08-07

申请号：US09583596

申请日：2000-05-31

申请人： Gerhard Mueller ,  Toshiaki Kirihata ,  Dmitry Netis

发明人： Gerhard Mueller ,  Toshiaki Kirihata ,  Dmitry Netis

IPC分类号： G11C800

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097

摘要： There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups; at least one sense amplifier; a first and a second multiplexer; and at least one programmable control device. Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.

摘要翻译： 提供一种半导体存储器件，其包括：以至少两组布置的多个存储单元; 至少一个读出放大器; 第一和第二多路复用器; 和至少一个可编程控制装置。 每个多路复用器适于将至少一个组耦合到放大器。 可编程控制装置适于控制第一和第二多路复用器。 在一个实施例中，可编程控制装置适于独立地控制多路复用器。

公开(公告)号：US06477630B2

公开(公告)日：2002-11-05

申请号：US09257146

申请日：1999-02-24

申请人： Brian Ji ,  Toshiaki Kirihata ,  Dmitry Netis

发明人： Brian Ji ,  Toshiaki Kirihata ,  Dmitry Netis

IPC分类号： G06F1300

CPC分类号： G11C11/4097 ,  G11C11/4087

摘要： A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.

摘要翻译： 存储器结构包括多个存储体（每个存储体包括多个块）连接到相应存储体中的所有块的多个时序关键地址线（关键地址线的数量等于 银行数量）以及连接到各个块的多个专用地址线。

公开(公告)号：US06690198B2

公开(公告)日：2004-02-10

申请号：US10114195

申请日：2002-04-02

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： H03K190175

CPC分类号： H03K19/01721 ,  G11C7/1048 ,  G11C7/1069 ,  G11C11/4096 ,  H03K19/0013

摘要： A repeater circuit having improved switching speed and reduced power consumption is described. The repeater circuit is configured to receive an input signal from a first segment of a signal line and pass the signal to a second segment of the signal line in response to an active control signal.

摘要翻译： 描述了具有改进的开关速度和降低的功耗的中继器电路。 中继器电路被配置为从信号线的第一段接收输入信号，并且响应于主动控制信号将信号传递到信号线的第二段。

公开(公告)号：US5831912A

公开(公告)日：1998-11-03

申请号：US938074

申请日：1997-09-26

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/18 ,  G11C11/409 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00 ,  G11C7/02

CPC分类号： G11C5/025 ,  G11C11/4097 ,  G11C7/18

摘要： The present disclosure includes semiconductor memory with a space efficient layout. Dynamic Random Access Memory (DRAM) chips have a plurality of memory cells (18) arranged in rows and columns. A semiconductor memory includes a bank of sense amplifiers (14) disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier (14) in the bank disposed in a sense amplifier region of an associated column (16). A plurality of amplifiers (124 or 126) are driven by at least one driver (140 or 142), each of the plurality of amplifiers disposed between a pair of complementary bit lines (120) and located within the sense amplifier region. The at least one driver shares at least one diffusion region extending transversely to the column direction with at least on other driver such that the number of contacts of the sense amplifier bank is reduced.

摘要翻译： 本公开包括具有空间有效布局的半导体存储器。 动态随机存取存储器（DRAM）芯片具有以行和列排列的多个存储单元（18）。 半导体存储器包括设置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中每个读出放大器（14）设置在相关联的列（16）的读出放大器区域中， 。 多个放大器（124或126）由至少一个驱动器（140或142）驱动，多个放大器中的每个放大器设置在一对互补位线（120）之间并位于读出放大器区域内。 至少一个驱动器至少与至少一个驱动器共享至少一个横向于列方向延伸的扩散区域，使得读出放大器组的触点数量减少。

公开(公告)号：US07146471B2

公开(公告)日：2006-12-05

申请号：US10748333

申请日：2003-12-31

申请人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

发明人： Toshiaki Kirihata ,  Gerhard Mueller ,  Wing K. Luk

IPC分类号： G06F12/02

CPC分类号： G06F13/1694 ,  Y02D10/14

摘要： A memory system that employs simultaneous activation of at least two dissimilar memory arrays, during a data manipulation, such as read or write operations is disclosed. An exemplary embodiment includes a memory system containing a plurality of arrays, each in communication with a common controller, wherein the arrays are activated by different supply voltage (Vdd). When a processor sends a command to retrieve or write data to the memory system, two or more arrays are addressed to supply the required data. By proper partitioning of the data between dissimilar arrays, the efficiency of data reading is improved.

摘要翻译： 公开了一种在诸如读取或写入操作的数据操作期间同时激活至少两个不同的存储器阵列的存储器系统。 示例性实施例包括包含多个阵列的存储器系统，每个阵列与公共控制器通信，其中阵列由不同的电源电压（Vdd）激活。 当处理器发送命令以检索或写入数据到存储器系统时，寻址两个或更多个阵列以提供所需的数据。 通过在不同阵列之间适当分割数据，数据读取的效率得到提高。

公开(公告)号：US6081479A

公开(公告)日：2000-06-27

申请号：US333539

申请日：1999-06-15

申请人： Brian Ji ,  Toshiaki Kirihata ,  Gerhard Mueller ,  David Hanson

发明人： Brian Ji ,  Toshiaki Kirihata ,  Gerhard Mueller ,  David Hanson

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1039

摘要： A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.

摘要翻译： 根据本发明的半导体存储器包括包括多个分层级的数据路径，每个级包括与其他级不同的位数据速率。 至少两个预取电路设置在各级之间。 至少两个预取电路包括用于接收数据位并存储数据位的至少两个锁存器，直到层级中的下一级能够接收数据位。 所述至少两个预取电路耦合在级之间，使得级之间每级的总体数据速率基本相等。 控制信号控制至少两个锁存器，使得预取电路保持级之间的总体数据速率。

公开(公告)号：US5877994A

公开(公告)日：1999-03-02

申请号：US938073

申请日：1997-09-26

申请人： Gerhard Mueller ,  Toshiaki Kirihata

发明人： Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： G11C11/403 ,  G11C7/06 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/02 ,  G11C5/02 ,  G11C5/06 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C7/065

摘要： A semiconductor memory having a plurality of memory cells arranged in rows and columns includes a bank of sense amplifiers disposed in a first generally rectangular region having a length parallel to said rows, with each sense amplifier in the bank disposed in a sense amplifier region between a pair of complementary bit lines of an associated column. An MDQ switch being located in a sense amplifier region occupying a corresponding row-wise space to the at least one driver to provide space efficient placement thereof.

摘要翻译： 具有排列成行和列的多个存储单元的半导体存储器包括布置在具有与所述行平行的长度的第一大致矩形区域中的读出放大器组，其中存储体中的每个读出放大器设置在读出放大器区域之间， 一对相关列的互补位线。 MDQ开关位于感测放大器区域中，占据与至少一个驱动器相对应的行方向空间以提供空间高效的放置。

公开(公告)号：US5864496A

公开(公告)日：1999-01-26

申请号：US939455

申请日：1997-09-29

申请人： Gerhard Mueller ,  Toshiaki Kirihata ,  Heinz Hoenigschmid

发明人： Gerhard Mueller ,  Toshiaki Kirihata ,  Heinz Hoenigschmid

IPC分类号： H01L27/108 ,  G11C7/18 ,  G11C11/4097 ,  H01L21/8242 ,  G11C5/08

CPC分类号： H01L27/10891 ,  G11C11/4097 ,  G11C7/18 ,  H01L27/10861

摘要： The semiconductor memory includes a memory cell array (10) of memory cells arranged in rows and columns, and a plurality of diagonal bit lines (BLP.sub.1 -BLP.sub.N) arranged in a pattern that changes horizontal direction along the memory cell array to facilitate access to said memory cells. The bit lines are arranged non-orthogonal to a plurality of dual word lines (WL.sub.1 -WL.sub.M), where each dual word line includes a master word line (MWL.sub.i) at a first layer and a plurality of local word lines (LWL.sub.1 -LWL.sub.X) at a second layer. The local word lines are connected to the master word line of a common row via a plurality of spaced electrical connections (29), e.g., electrical contacts in a "stitched" architecture, and each local word line is connected to plural memory cells (MC). The electrical connections run in substantially the same pattern along the memory cell array as the bit lines.

摘要翻译： 半导体存储器包括以行和列排列的存储器单元的存储单元阵列（10）和以沿存储单元阵列改变水平方向的图案布置的多个对角位线（BLP1-BLPN），以便于访问所述 记忆细胞 位线布置成与多条双字线（WL1-WLM）非正交，其中每个双字线包括第一层的主字线（MWLi）和多个本地字线（LWL1-LWLX） 在第二层。 本地字线经由多个间隔的电连接（29）连接到公共行的主字线，例如“缝合”结构中的电触点，并且每个本地字线连接到多个存储单元（MC ）。 电连接沿着与位线的存储单元阵列基本上相同的图案运行。

公开(公告)号：US06683486B2

公开(公告)日：2004-01-27

申请号：US10114221

申请日：2002-04-02

申请人： David Hanson ,  Gerhard Mueller ,  Toshiaki Kirihata

发明人： David Hanson ,  Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： H03L500

CPC分类号： H03K3/356147 ,  H03K3/012

摘要： A low voltage level shifter circuit with an embedded latch, implemented on a signal line having thereon low voltage signals. There is included a low voltage level shifter circuit configured to receive a low voltage input signal from a first portion of the signal line and output a higher voltage output signal on a second portion of the signal line. A latching circuit is also included, and is configured to latch the low voltage input signal from the first portion of the signal line.

摘要翻译： 具有嵌入式锁存器的低电压电平移位器电路，其在具有低电压信号的信号线上实现。 包括低电压电平移位器电路，其配置为从信号线的第一部分接收低电压输入信号，并在信号线的第二部分上输出更高电压的输出信号。 还包括锁存电路，并且被配置为锁存来自信号线的第一部分的低电压输入信号。

公开(公告)号：US06370055B1

公开(公告)日：2002-04-09

申请号：US09795761

申请日：2001-02-28

申请人： David Hanson ,  Gerhard Mueller ,  Toshiaki Kirihata

发明人： David Hanson ,  Gerhard Mueller ,  Toshiaki Kirihata

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： There is provided a semiconductor memory having a plurality of memory units. The memory includes a plurality of read write drive (RWD) lines horizontally and/or vertically twisted such that the RWD lines are shared between the plurality of memory units. A plurality of columns is included in each of the plurality of memory units. Each of the plurality of columns is adapted to access the plurality of RWD lines through asymmetrical addressing.

摘要翻译： 提供了具有多个存储单元的半导体存储器。 存储器包括水平和/或垂直扭转的多个读写驱动（RWD）线，使得RWD线在多个存储器单元之间共享。 在多个存储单元的每一个中包括多个列。 多个列中的每一个适于通过非对称寻址来访问多个RWD线。