公开(公告)号：US07778351B2

公开(公告)日：2010-08-17

申请号：US10118750

申请日：2002-04-09

申请人： Louis L. Hsu ,  Li-Kong Wang ,  Philip J. Murfet

发明人： Louis L. Hsu ,  Li-Kong Wang ,  Philip J. Murfet

IPC分类号： H03F3/26 ,  H03F3/68 ,  H03F3/04 ,  H04L25/03

CPC分类号： H03K19/00384

摘要： A CMOS receiver system having a tunable receiver having a tunable gain and a bandwidth system is provided. The tunable receiver includes means for receiving input signals; and a control circuit controlled by a control signal for tuning at least one of the gain and the bandwidth of the tunable receiver, wherein the control signal is indicative of a data rate of the input signals. Furthermore, a method is provided for tuning a CMOS receiver receiving input signals. The method includes the steps of receiving at least one control signal, and controlling one of gain and bandwidth of the CMOS receiver in accordance with the at least one control signal, wherein the at least one control signal is indicative of a data rate of the received input signals.

摘要翻译： 提供具有可调谐增益和带宽系统的可调谐接收机的CMOS接收机系统。 可调谐接收机包括用于接收输入信号的装置; 以及由控制信号控制的控制电路，用于调谐可调接收机的增益和带宽中的至少一个，其中控制信号表示输入信号的数据速率。 此外，提供了一种用于调谐接收输入信号的CMOS接收器的方法。 该方法包括以下步骤：接收至少一个控制信号，并根据至少一个控制信号控制CMOS接收机的增益和带宽中的一个，其中至少一个控制信号指示接收的数据速率 输入信号。

公开(公告)号：US07519130B2

公开(公告)日：2009-04-14

申请号：US10905705

申请日：2005-01-18

申请人： Louis L. Hsu ,  Matt R. Cordrey-Gale ,  James S. Mason ,  Philip J. Murfet ,  Karl D. Selander ,  Michael A. Sorna ,  Huihao Xu

发明人： Louis L. Hsu ,  Matt R. Cordrey-Gale ,  James S. Mason ,  Philip J. Murfet ,  Karl D. Selander ,  Michael A. Sorna ,  Huihao Xu

IPC分类号： H04L25/34

CPC分类号： H04L25/0274 ,  H04L25/0296

摘要： A data receiver is provided which includes a front end interface circuit having an alternating current (AC) transmission receiving mode and a direct current (DC) transmission receiving mode. The front end interface circuit includes an offset compensation circuit operable to compensate a DC voltage offset between a pair of differential signals input to the data receiver. The front end interface circuit further includes an AC/DC selection unit operable to switch between (a) the DC transmission receiving mode, and (b) the AC transmission receiving mode, such that the data receiver is operable in (i) the DC transmission mode in which the offset compensation circuit is disabled, (ii) the DC transmission mode in which the offset compensation circuit is enabled, (iii) the AC transmission mode in which the offset compensation circuit is disabled, and (iv) the AC transmission receiving mode in which the offset compensation circuit is enabled.

摘要翻译： 提供一种数据接收器，其包括具有交流（AC）发送接收模式和直流（DC）发送接收模式的前端接口电路。 前端接口电路包括偏移补偿电路，其可操作以补偿输入到数据接收器的一对差分信号之间的直流电压偏移。 前端接口电路还包括可操作以在（a）直流发送接收模式和（b）交流发送接收模式之间切换的AC / DC选择单元，使得数据接收器可操作于（i）直流传输 偏移补偿电路被禁用的模式，（ii）使能偏移补偿电路的直流传输模式，（iii）偏移补偿电路被禁用的AC传输模式，以及（iv）AC传输接收 偏移补偿电路使能的模式。

公开(公告)号：US07052937B2

公开(公告)日：2006-05-30

申请号：US10429758

申请日：2003-05-05

申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Li-Kong Wang ,  Tsorng-Dih Yuan

IPC分类号： H01L21/44

CPC分类号： H01L21/76264 ,  H01L21/76283 ,  H01L23/3677 ,  H01L23/3732 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure. Yet another embodiment comprises diamond sidewalls formed along the device walls in thermal contact with the device junctions to provide heat dissipation through the device junctions to underlying cooling structures. It is also proposed that the foregoing structures, and combinations of the foregoing structures, could be used in conjunction with other known cooling schemes.

公开(公告)号：US07029956B2

公开(公告)日：2006-04-18

申请号：US10666972

申请日：2003-09-19

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L21/332

CPC分类号： H01L27/1027 ,  H01L21/8213 ,  H01L27/0605 ,  Y10S438/931

摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

公开(公告)号：US06911375B2

公开(公告)日：2005-06-28

申请号：US10452715

申请日：2003-06-02

申请人： Kathryn W. Guarini ,  Louis L. Hsu ,  Leathen Shi ,  Dinkar V. Singh ,  Li-Kong Wang

发明人： Kathryn W. Guarini ,  Louis L. Hsu ,  Leathen Shi ,  Dinkar V. Singh ,  Li-Kong Wang

IPC分类号： H01L21/30 ,  H01L21/68 ,  H01L21/762

CPC分类号： H01L21/76256 ,  H01L21/6835 ,  H01L21/76254 ,  H01L2221/68368 ,  H01L2924/19041

摘要： Described is a method for making silicon on sapphire structures, and devices therefrom. The inventive method of forming integrated circuits on a sapphire substrate comprises the steps of providing a device layer on an oxide layer of a temporary substrate; bonding the device layer to a handling substrate; removing the temporary substrate to provide a structure containing the device layer between the oxide layer and the handling substrate; bonding a sapphire substrate to the oxide layer; removing the handling substrate from the structure; and annealing the final structure to provide a substrate comprising the oxide layer between the device layer and the sapphire substrate. The sapphire substrate may comprise bulk sapphire or may be a conventional substrate material with an uppermost sapphire layer.

摘要翻译： 描述了在蓝宝石结构上制造硅的方法及其装置。 在蓝宝石衬底上形成集成电路的本发明的方法包括以下步骤：在临时衬底的氧化物层上提供器件层; 将所述器件层接合到处理衬底; 去除所述临时衬底以提供在所述氧化物层和所述处理衬底之间包含所述器件层的结构; 将蓝宝石衬底结合到氧化物层; 从结构中去除处理基板; 并退火最终结构以提供包括在器件层和蓝宝石衬底之间的氧化物层的衬底。 蓝宝石衬底可以包括散装蓝宝石，或者可以是具有最上层蓝宝石层的常规衬底材料。

公开(公告)号：US06781185B2

公开(公告)日：2004-08-24

申请号：US10091193

申请日：2002-03-05

申请人： Howard Hao Chen ,  Louis L. Hsu ,  Li-Kong Wang

发明人： Howard Hao Chen ,  Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L23/5222 ,  H01L27/0805 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

摘要： Apparatus and method for providing high dielectric constant decoupling capacitors for semiconductor structures. The high dielectric constant decoupling capacitor can be fabricated by depositing high dielectric constant material between adjacent conductors on the same level, between conductors in successive levels, or both, to thereby provide very large capacitance value without any area or reliability penalty.

摘要翻译： 用于为半导体结构提供高介电常数去耦电容器的装置和方法。 高介电常数去耦电容器可以通过在相同电平上的相邻导体之间，连续电平的导体之间沉积高介电常数材料或两者来制造，从而提供非常大的电容值而没有任何面积或可靠性损失。

公开(公告)号：US06697909B1

公开(公告)日：2004-02-24

申请号：US09660431

申请日：2000-09-12

申请人： Li-Kong Wang ,  Louis L. Hsu

发明人： Li-Kong Wang ,  Louis L. Hsu

IPC分类号： G06F1300

CPC分类号： G11C11/40603 ,  G06F12/0802 ,  G11C11/406 ,  G11C11/40607

摘要： A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.

摘要翻译： 提供了一种用于刷新计算机系统中的动态随机存取存储器（DRAM）高速缓冲存储器中的数据的方法和装置，用于执行数据刷新操作而不刷新（例如处理器中的延迟）。 通过检测来自处理器的请求地址，当检测到请求地址时停止正常刷新操作，将请求地址与存储在TAG存储器中的TAG地址进行比较，生成刷新地址 刷新存储在高速缓冲存储器中的数据，其中每个基于与刷新地址相对应的数据的年龄生成，并且对由请求地址访问的字线执行读/写操作，并且通过刷新访问的字线刷新数据 地址，其中同时执行读/写操作和数据刷新。

公开(公告)号：US06627924B2

公开(公告)日：2003-09-30

申请号：US09845695

申请日：2001-04-30

申请人： Louis L. Hsu ,  Li-Kong Wang

发明人： Louis L. Hsu ,  Li-Kong Wang

IPC分类号： H01L2974

CPC分类号： H01L27/1027 ,  H01L21/8213 ,  H01L27/0605 ,  Y10S438/931

摘要： A memory system having a plurality of T-RAM cells arranged in an array is presented where each T-RAM cell has dual vertical devices and is fabricated over a SiC substrate. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure over the SiC substrate.

公开(公告)号：US06512683B2

公开(公告)日：2003-01-28

申请号：US09827071

申请日：2001-04-05

申请人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata

发明人： Louis L. Hsu ,  Li-Kong Wang ,  Toshiaki K. Kirihata

IPC分类号： G11C1500

CPC分类号： G06F12/0895 ,  G06F12/0846 ,  G11C7/1042

摘要： The speed of memories is increased by trading memory density (or area) for speed (or cycle time). An n by n memory array is used to reduce the memory cycle time by 1/n. For example, if an existing memory cycle time is 6 ns, in order to achieve a 3ns (or n=2) cycle time, a 2 by 2 memory array is used. Or, in order to achieve a 1ns cycle time (or n=6), then a 6 by 6 memory array is used.

摘要翻译： 通过为速度（或循环时间）交易记忆密度（或面积）来提高记忆速度。 n n存储器阵列用于将存储器周期时间减少1 / n。 例如，如果现有存储器周期时间为6ns，为了实现3ns（或n = 2）周期时间，则使用2乘2存储器阵列。 或者，为了实现1ns周期时间（或n = 6），则使用6乘6存储器阵列。

公开(公告)号：US06307805B1

公开(公告)日：2001-10-23

申请号：US09745227

申请日：2000-12-21

申请人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

发明人： John E. Andersen ,  Terence B. Hook ,  Louis L. Hsu ,  Wei Hwang ,  Stephen V. Kosonocky ,  Li-Kong Wang

IPC分类号： G11C700

CPC分类号： G11C8/08 ,  G11C11/418 ,  H01L27/11

摘要： A semiconductor memory device accessed with wordlines and bitlines has memory cells which operate at high performance with lower power consumption and have a high density. Each of the memory cells has pass transistors connected to a corresponding wordline and a corresponding pair of bitlines, and the pass transistors are gated by a signal of the corresponding wordline. The semiconductor memory device includes a wordline drive unit for selectively driving the wordlines in response to a row address. A wordline driver in the wordline drive unit boosts a corresponding wordline in a positive direction when the corresponding wordline is activated to access the memory cell and boosts the corresponding wordline in a negative direction when the corresponding wordline is inactive. By boosting the wordline in the positive direction, the performance of the memory cells is enhanced, and by boosting the wordline in the negative direction, a leakage current in the pass transistors with a low-threshold voltage is prevented.

摘要翻译： 用字线和位线访问的半导体存储器件具有以较低的功耗以高密度工作的高性能的存储单元。 每个存储单元具有连接到相应字线和相应的一对位线的传输晶体管，并且通过晶体管由相应字线的信号选通。 半导体存储器件包括用于响应于行地址选择性地驱动字线的字线驱动单元。 当对应的字线不活动时，字线驱动单元中的字线驱动器在相应的字线被激活以访问存储器单元并且在相反的方向上升高相应的字线时以正方向提升相应的字线。 通过在正方向上升压字线，增强了存储单元的性能，并且通过在负方向上升高字线，防止具有低阈值电压的通过晶体管中的漏电流。