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    POWER-DOWN/POWER-LOSS MEMORY CONTROLLER
    2.
    发明申请
    POWER-DOWN/POWER-LOSS MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20190042156A1

    公开(公告)日：2019-02-07

    申请号：US15986804

    申请日：2018-05-22

    申请人： Luca De Santis ,  Tommaso Vali ,  Luca Nubile ,  Ricardo Cardinali ,  Maria L. Gallese ,  Cristina Lattaro

    发明人： Luca De Santis ,  Tommaso Vali ,  Luca Nubile ,  Ricardo Cardinali ,  Maria L. Gallese ,  Cristina Lattaro

    IPC分类号： G06F3/06

    摘要： Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

    Chip protection register lock circuit in a flash memory device
    3.
    发明申请
    Chip protection register lock circuit in a flash memory device 有权
    芯片保护寄存器锁定电路在闪存设备中

    公开(公告)号：US20070038828A1

    公开(公告)日：2007-02-15

    申请号：US11583675

    申请日：2006-10-19

    申请人： Luca De Santis ,  Tommaso Vali

    发明人： Luca De Santis ,  Tommaso Vali

    IPC分类号： G06F12/14 ,  G06F12/00

    CPC分类号： G11C16/22

    摘要： A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are coupled to an erase circuit and the remaining N/2 bits are coupled to a programming circuit. After the chip protection register is programmed, the group of N/2 bits coupled to the erase circuit are erased and the remaining N/2 bits are programmed such that an alternating pattern of logical ones and zeros are in the lock bit register. A read and compare circuit generates a lock indication if the alternating pattern is present.

    摘要翻译： 芯片保护寄存器锁定电路在锁定位寄存器中使用多个锁定位。 如果寄存器包含N位，则寄存器的N / 2位耦合到擦除电路，剩余的N / 2位耦合到编程电路。 在编程芯片保护寄存器之后，擦除与擦除电路相关的N / 2位的组，并对其余的N / 2位进行编程，使得逻辑1和0的交替模式位于锁定位寄存器中。 如果存在交替模式，则读取和比较电路产生锁定指示。

    High voltage low power sensing device for flash memory
    4.
    发明授权
    High voltage low power sensing device for flash memory 有权
    用于闪存的高电压低功率感测装置

    公开(公告)号：US06914821B2

    公开(公告)日：2005-07-05

    申请号：US10696688

    申请日：2003-10-29

    申请人： Tommaso Vali ,  Luca De Santis

    发明人： Tommaso Vali ,  Luca De Santis

    IPC分类号： G11C7/06 ,  G11C16/26 ,  G11C16/28

    CPC分类号： G11C16/26 ,  G11C7/062 ,  G11C7/067

    摘要： Sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-power memory devices using supply potentials that can be significantly higher than the maximum potential to be achieved on a local bit line during a sensing operation. Such sensing devices include an input node selectively coupled to a floating-gate memory cell and an output node for providing an output signal indicative of the programmed state of the floating-gate memory cell. Such sensing devices further include a feedback loop coupled between a precharge path and the input node of the sensing device. The feedback loop limits the potential level achieved at the input node of the sensing device, thus limiting the potential level achieved by the bit lines during sensing.

    摘要翻译： 用于感测浮栅存储器单元的编程状态的感测装置适用于使用能够显着高于在感测操作期间在局部位线上实现的最大电位的电源电位的低功率存储器件。 这样的感测装置包括选择性地耦合到浮动栅极存储器单元的输入节点和用于提供指示浮动栅极存储器单元的编程状态的输出信号的输出节点。 这种感测装置还包括耦合在预充电路径和感测装置的输入节点之间的反馈回路。 反馈环路限制了在感测装置的输入节点处实现的电位电平，从而限制了感测期间由位线实现的电位电平。

    DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY
    5.
    发明申请
    DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY 有权
    动态SLC / MLC块分配非易失性存储器

    公开(公告)号：US20100122016A1

    公开(公告)日：2010-05-13

    申请号：US12269766

    申请日：2008-11-12

    申请人： Giulio Marotta ,  Luca De Santis ,  Tommaso Vali

    发明人： Giulio Marotta ,  Luca De Santis ,  Tommaso Vali

    IPC分类号： G06F12/02 ,  G06F12/00

    CPC分类号： G11C16/16 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C2211/5641

    摘要： Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

    摘要翻译： 公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。 在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。 当内存使用量低时，使用SLC模式。 当内存使用率高时，使用MLC模式。 动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。

    High voltage low power sensing device for flash memory
    6.
    发明授权
    High voltage low power sensing device for flash memory 有权
    用于闪存的高电压低功率感测装置

    公开(公告)号：US06671206B2

    公开(公告)日：2003-12-30

    申请号：US10229399

    申请日：2002-08-27

    申请人： Tommaso Vali ,  Luca De Santis

    发明人： Tommaso Vali ,  Luca De Santis

    IPC分类号： G11C1626

    CPC分类号： G11C16/26 ,  G11C7/062 ,  G11C7/067

    摘要： Sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-power memory devices using supply potentials that can be significantly higher than the maximum potential to be achieved on a local bit line during a sensing operation. Such sensing devices include an input node selectively coupled to a floating-gate memory cell and an output node for providing an output signal indicative of the programmed state of the floating-gate memory cell. Such sensing devices further include a feedback loop coupled between a precharge path and the input node of the sensing device. The feedback loop limits the potential level achieved at the input node of the sensing device, thus limiting the potential level achieved by the bit lines during sensing.

    摘要翻译： 用于感测浮栅存储器单元的编程状态的感测装置适用于使用能够显着高于在感测操作期间在局部位线上实现的最大电位的电源电位的低功率存储器件。 这样的感测装置包括选择性地耦合到浮动栅极存储器单元的输入节点和用于提供指示浮动栅极存储器单元的编程状态的输出信号的输出节点。 这种感测装置还包括耦合在预充电路径和感测装置的输入节点之间的反馈回路。 反馈环路限制了在感测装置的输入节点处实现的电位电平，从而限制了感测期间由位线实现的电位电平。

    Power down/power-loss memory controller
    8.
    发明授权
    Power down/power-loss memory controller 有权

    公开(公告)号：US10528292B2

    公开(公告)日：2020-01-07

    申请号：US15986804

    申请日：2018-05-22

    申请人： Luca De Santis ,  Tommaso Vali ,  Luca Nubile ,  Ricardo Cardinali ,  Maria L. Gallese ,  Cristina Lattaro

    发明人： Luca De Santis ,  Tommaso Vali ,  Luca Nubile ,  Ricardo Cardinali ,  Maria L. Gallese ,  Cristina Lattaro

    IPC分类号： G11C16/04 ,  G06F3/06 ,  G06F1/26

    摘要： Embodiments of the present disclosure may relate to a memory controller that may include a main controller to begin a power down of a non-volatile memory storage during a first time period, while operating in a first voltage range, wherein the main controller is to begin the power down of the non-volatile memory in response to an indication of a voltage level being below a predetermined threshold; and a sequencer to continue the power down of the memory storage during a second time period, while operating within a second voltage range lower than the first voltage range. In some embodiments, the sequencer may include a state machine to perform a discharge sequence, where the state machine includes a micro-action output to output a micro-action command to the memory storage based at least in part on a current state of the state machine. Other embodiments may be described and/or claimed.

    Chip protection register lock circuit in a flash memory device
    9.
    发明授权
    Chip protection register lock circuit in a flash memory device 有权
    芯片保护寄存器锁定电路在闪存设备中

    公开(公告)号：US07143255B2

    公开(公告)日：2006-11-28

    申请号：US10854397

    申请日：2004-05-26

    申请人： Luca De Santis ,  Tommaso Vali

    发明人： Luca De Santis ,  Tommaso Vali

    IPC分类号： G06F12/14

    CPC分类号： G11C16/22

    摘要： A chip protection register lock circuit uses a plurality of lock bits in a lock bit register. If the register contains N bits, N/2 bits of the register are coupled to an erase circuit and the remaining N/2 bits are coupled to a programming circuit. After the chip protection register is programmed, the group of N/2 bits coupled to the erase circuit are erased and the remaining N/2 bits are programmed such that an alternating pattern of logical ones and zeros are in the lock bit register. A read and compare circuit generates a lock indication if the alternating pattern is present.

    摘要翻译： 芯片保护寄存器锁定电路在锁定位寄存器中使用多个锁定位。 如果寄存器包含N位，则寄存器的N / 2位耦合到擦除电路，剩余的N / 2位耦合到编程电路。 在编程芯片保护寄存器之后，擦除与擦除电路相关的N / 2位的组，并对其余的N / 2位进行编程，使得逻辑1和0的交替模式位于锁定位寄存器中。 如果存在交替模式，则读取和比较电路产生锁定指示。

    Dynamic SLC/MLC blocks allocations for non-volatile memory
    10.
    发明授权
    Dynamic SLC/MLC blocks allocations for non-volatile memory 有权
    动态SLC / MLC阻止非易失性存储器的分配

    公开(公告)号：US08407400B2

    公开(公告)日：2013-03-26

    申请号：US12269766

    申请日：2008-11-12

    申请人： Giulio Marotta ,  Luca De Santis ,  Tommaso Vali

    发明人： Giulio Marotta ,  Luca De Santis ,  Tommaso Vali

    IPC分类号： G06F12/00

    CPC分类号： G11C16/16 ,  G06F12/0246 ,  G06F2212/7202 ,  G11C2211/5641

    摘要： Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode.

    摘要翻译： 公开了装置和方法，例如基于特性在单级单元（SLC）和多级单元（MLC）之间的NAND闪速存储器中提供动态块分配的装置和方法。 在一个实施例中，存储器控制器基于可用于使用的存储器的量，在SLC模式和MLC模式之间的编程和/或重新编程块之间动态切换。 当内存使用量低时，使用SLC模式。 当内存使用率高时，使用MLC模式。 动态块分配允许内存控制器获得SLC模式的性能和可靠性优势，同时保持MLC模式的节省空间的优势。