公开(公告)号：US6094022A

公开(公告)日：2000-07-25

申请号：US346650

申请日：1999-07-01

申请人： Luca Schillaci ,  Maurizio Nessi ,  Giacomino Bollati ,  Ezio Galbiati

发明人： Luca Schillaci ,  Maurizio Nessi ,  Giacomino Bollati ,  Ezio Galbiati

IPC分类号： H02P6/18 ,  H02K23/00

CPC分类号： H02P6/182

摘要： A BEMF detector and method detect the BEMF of a three-phase motor using a fully differential detection system. The motor has a first coil coupled between a first coil tap and a center tap, a second coil coupled between a second coil tap and the center tap, and a third coil coupled between a third coil tap and the center tap. The BEMF detector includes a differential amplifier having first and second inputs and first and second outputs, with the first input being coupled to one of the coil taps and the second input being coupled to the center tap. The BEMF detector also includes a comparator having first and second inputs coupled respectively to the first and second outputs of the differential amplifier and an output at which a BEMF signal is produced that is related to the BEMF of the motor. The differential amplifier may be part of an anti-alias filter structured to fix to a known stable value a common mode at the outputs of the differential amplifier. The BEMF detector also may include one or more fully differential filters positioned between the differential amplifier and the comparator to reduce noise and smooth the BEMF signal output by the comparator. One of the filters can be a linear phase, switched capacitor filter with a stable cutoff frequency.

摘要翻译： BEMF检测器和方法使用完全差分检测系统检测三相电机的BEMF。 电动机具有耦合在第一线圈抽头和中心抽头之间的第一线圈，耦合在第二线圈抽头和中心抽头之间的第二线圈以及耦合在第三线圈抽头和中心抽头之间的第三线圈。 BEMF检测器包括具有第一和第二输入以及第一和第二输出的差分放大器，其中第一输入耦合到线圈抽头之一并且第二输入耦合到中心抽头。 BEMF检测器还包括比较器，其具有分别耦合到差分放大器的第一和第二输出端的第一和第二输入端以及产生与马达的BEMF有关的BEMF信号的输出端。 差分放大器可以是抗差分滤波器的一部分，其被构造为在差分放大器的输出处固定到已知稳定值的共模。 BEMF检测器还可以包括位于差分放大器和比较器之间的一个或多个全差分滤波器，以降低噪声并平滑比较器输出的BEMF信号。 其中一个滤波器可以是具有稳定截止频率的线性相位开关电容滤波器。

公开(公告)号：US06208184B1

公开(公告)日：2001-03-27

申请号：US09451051

申请日：1999-11-30

申请人： Marco Demicheli ,  Melchiorre Bruccoleri ,  Maurizio Malfa ,  Giacomino Bollati

发明人： Marco Demicheli ,  Melchiorre Bruccoleri ,  Maurizio Malfa ,  Giacomino Bollati

IPC分类号： H03L700

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09

摘要： A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream. The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting the digital data stream from the second circuit directed to the write head. The transitions immediately following a preceding transition are delayed by the pre-established time interval, by sampling the two digital streams with a pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a certain different time interval.

摘要翻译： 提供了一种方法和电路，用于当在发生先前转换的时钟阶段发生转换时，将馈送到大容量存储设备的写入头的数字数据流中的转变延迟一定的时间间隔，以便 读取存储的数据时遇到的补偿前符号非线性干扰效应。 该方法包括将待存储的数字数据流和时钟信号馈送到第一电路，并从第一电路输出一对数字流。 每当在不连续输入流的转换的时钟相位的时钟相位期间，输入流的转变发生时，第一流假设第一逻辑值。 每当在输入流中发生转换的时钟相位之后的时钟相位期间，输入流的转变发生时，第二流假设第一逻辑值。 该方法还包括将两个数字流和时钟信号馈送到第二电路的输入，并从指向写入头的第二电路输出数字数据流。 通过用一对触发器对两个数字流进行采样来分别由分别延迟了某个不同的时间间隔的时钟信号定时，通过先前转换之后的转换被延迟预先建立的时间间隔。

公开(公告)号：US20080316906A1

公开(公告)日：2008-12-25

申请号：US12199207

申请日：2008-08-27

申请人： Giacomino Bollati ,  Alessandro Bosi ,  Giovanni Antonio Cesura

发明人： Giacomino Bollati ,  Alessandro Bosi ,  Giovanni Antonio Cesura

IPC分类号： G11B9/00

CPC分类号： B82Y10/00 ,  G11B5/86 ,  G11B9/02 ,  G11B9/1418 ,  G11B11/002

摘要： A transducer for a storage medium has a supporting element positioned over the storage medium with a first head configured to interact with the storage medium and a second head operatively connected to the first head to interact with the storage medium. The second head is carried by the supporting element in a position adjacent to the first head, and the first head and the second head are aligned in a scanning direction. The first head performs the reading of a data item stored in a portion of the storage medium, the reading entailing the deletion of the data item, and the second head performs the rewriting of the data item in the same portion of the storage medium.

摘要翻译： 用于存储介质的换能器具有位于存储介质上的支撑元件，其中第一头配置成与存储介质相互作用，第二头与第一头可操作地连接以与存储介质相互作用。 第二头部由支撑元件承载在与第一头部相邻的位置，第一头部和第二头部沿扫描方向排列。 第一头执行存储在存储介质的一部分中的数据项的读取，读取需要删除数据项，并且第二头在存储介质的相同部分中执行数据项的重写。

公开(公告)号：US06654192B1

公开(公告)日：2003-11-25

申请号：US09294642

申请日：1999-04-19

申请人： Melchiorre Bruccoleri ,  Daniele Ottini ,  Marco Demicheli ,  Giacomino Bollati

发明人： Melchiorre Bruccoleri ,  Daniele Ottini ,  Marco Demicheli ,  Giacomino Bollati

IPC分类号： G11B509

CPC分类号： G01R19/22

摘要： A full-wave rectifier for monitoring the amplitude of a differential analog signal includes a differential Track&Hold stage controlled by a first differential logic timing signal tracking the differential analog input signal during a tracking phase that corresponds to a high logic stage of the first differential timing signal. This produces a differential output signal that is a replica of the input signal and the signal is stored during a successive storing phase that corresponds to a low logic state of the first differential timing signal. A first differential output amplifier includes inputs coupled to the output of the Track&Hold stage. A differential bistable circuit, controlled by a second differential logic timing signal, includes inputs coupled to the differential outputs of the first amplifier and produces a third differential logic control signal. A second multiplexed amplifier, controlled by the third differential control signal, includes inputs coupled to the output of the Track&Hold stage and produces a differential analog signal having an amplitude function corresponding to the amplitude of the differential input signal. A timing circuit receives at an input a differential logic synchronizing signal and generates the first differential timing signal of the Track&Hold stage and the second differential timing signal of the bistable circuit.

摘要翻译： 用于监视差分模拟信号的幅度的全波整流器包括差分跟踪和保持级，该差分跟踪保持级由跟踪第一差分定时信号的高逻辑级的跟踪阶段期间的差分模拟输入信号的第一差分逻辑定时信号控制 。 这产生作为输入信号的副本的差分输出信号，并且在对应于第一差分定时信号的低逻辑状态的连续存储阶段期间存储信号。 第一差分输出放大器包括耦合到跟踪和保持级的输出的输入。 由第二差分逻辑定时信号控制的差分双稳态电路包括耦合到第一放大器的差分输出并输出第三差分逻辑控制信号的输入。 由第三差分控制信号控制的第二多路复用放大器包括耦合到跟踪和保持级的输出的输入，并且产生具有对应于差分输入信号的幅度的幅度函数的差分模拟信号。 定时电路在输入端接收差分逻辑同步信号，并产生跟踪和保持级的第一差分定时信号和双稳态电路的第二差分定时信号。

公开(公告)号：US20070247226A1

公开(公告)日：2007-10-25

申请号：US11711477

申请日：2007-02-26

申请人： Giacomino Bollati ,  Marco Bongiorni

发明人： Giacomino Bollati ,  Marco Bongiorni

IPC分类号： H03F3/16 ,  G11B5/00 ,  H03F1/26

CPC分类号： H03F3/45183 ,  G11B2005/0018 ,  H03F1/3211 ,  H03F2203/45454 ,  H03F2203/45508

摘要： A corrector circuit for correcting second harmonic distortions is provided. The corrector circuit includes a transconductance circuit having an input transconductance with a transresistance load for receiving a distorted voltage signal having a second harmonic component. The transconductance circuit is adapted to generate a corrected voltage signal having the second harmonic component that is reduced from the distorted voltage signal as a function of the input transconductance. The corrector circuit further includes biasing means for providing a biasing current to the transconductance circuit (with the input transconductance that depends on the biasing current). The biasing means includes means for providing a fixed component of the biasing current, means for providing a variable component of the biasing current (being a function of the distorted voltage signal according to a proportionality coefficient) and means for programming the proportionality coefficient.

摘要翻译： 提供了一种用于校正二次谐波失真的校正电路。 校正器电路包括跨导电路，其具有用于接收具有二次谐波分量的失真电压信号的具有跨阻载荷的输入跨导。 跨导电路适于产生具有作为输入跨导的函数的从失真电压信号减小的二次谐波分量的校正电压信号。 校正器电路还包括偏置装置，用于向跨导电路提供偏置电流（输入跨导取决于偏置电流）。 偏置装置包括用于提供偏置电流的固定分量的装置，用于提供偏置电流的可变分量（根据比例系数作为失真电压信号的函数）的装置和用于对比例系数进行编程的装置。

公开(公告)号：US20050052216A1

公开(公告)日：2005-03-10

申请号：US10931469

申请日：2004-09-01

申请人： Marco Gaeta ,  Giacomino Bollati ,  Marco Bongiorni

发明人： Marco Gaeta ,  Giacomino Bollati ,  Marco Bongiorni

IPC分类号： H03G7/00 ,  H03G7/06 ,  G06G7/24

CPC分类号： H03G7/06 ,  H03G7/001

摘要： A logarithmic linear variable gain CMOS amplifier includes first and second differential pairs of transistors forming a differential input, with each differential pair of transistors including a common source node. A pair of diode-connected load transistors is connected to the first and second differential pairs of transistors, and a third differential pair of transistors is connected to the pair of diode-connected load transistors. The third differential pair of transistors include respective gates connected together and in parallel to gates of the first and second differential pairs of transistors. First and second current mirrors are respectively connected to the common source nodes of the first and second differential pairs of transistors for programmably injecting respective bias currents thereto, with a sum of the respective bias currents remaining constant.

摘要翻译： 对数线性可变增益CMOS放大器包括形成差分输入的晶体管的第一和第二差分对，每个晶体管的差分对包括公共源节点。 一对二极管连接的负载晶体管连接到第一和第二差分对晶体管，并且第三差分对晶体管连接到该对二极管连接的负载晶体管。 第三差分对晶体管包括连接在一起并与第一和第二差分对晶体管的栅极并联的各个栅极。 第一和第二电流镜分别连接到第一和第二差分晶体管对的共同源极节点，用于可编程地将相应的偏置电流注入其中，各个偏置电流的和保持恒定。

公开(公告)号：US06369741B1

公开(公告)日：2002-04-09

申请号：US09611695

申请日：2000-07-07

申请人： Marco Demicheli ,  Giacomino Bollati ,  Davide Demicheli ,  Stefano Marchese

发明人： Marco Demicheli ,  Giacomino Bollati ,  Davide Demicheli ,  Stefano Marchese

IPC分类号： H03M112

CPC分类号： G11B20/10481 ,  G11B20/10009 ,  G11B20/10037

摘要： A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

摘要翻译： 提供了一种用于定义用于磁性介质大容量存储器件的读取通道的预均衡的低通滤波器的升压和截止频率参数的编程值的方法，以确保最终的自适应滤波器的最佳功能条件 均衡 该方法包括预编程用于每个磁介质的预均衡低通滤波器的升压和截止频率参数的瞬时数字值，作为实现确定性的自适应滤波器的有意识的瞬时操作参数的函数 在磁性介质的修剪扫描期间信号的均衡。

公开(公告)号：US06346905B1

公开(公告)日：2002-02-12

申请号：US09447065

申请日：1999-11-22

申请人： Daniele Ottini ,  Melchiorre Bruccoleri ,  Giacomino Bollati ,  Marco Demicheli

发明人： Daniele Ottini ,  Melchiorre Bruccoleri ,  Giacomino Bollati ,  Marco Demicheli

IPC分类号： H03M1300

CPC分类号： H03M1/0809 ,  H03M1/365

摘要： A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

摘要翻译： 闪存模数转换器包括具有差分输出的一组比较器，产生测温代码和一组三输入逻辑或非门。 通过提供包括多个分压器的无源接口，每个连接在相应比较器的非反相输出端和该组的较高阶比较器的反相输出端之间，该转换器具有增强的抗噪声能力和减小的不精确性。 该组的对应逻辑或非门具有耦合到相应比较器的反相输出的第一输入，耦合到高阶比较器的非反相输出的第二输入和耦合到分压器的中间节点的第三输入。

公开(公告)号：US07078968B2

公开(公告)日：2006-07-18

申请号：US10939303

申请日：2004-09-10

申请人： Marco Gaeta ,  Giacomino Bollati

发明人： Marco Gaeta ,  Giacomino Bollati

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F1/3211 ,  H03F3/45623 ,  H03G1/0088

摘要： A step gain-variable CMOS amplifier includes an input pair of transistors, a bias current generator connected between a common source node of the input pair of transistors and a ground node, and a pair of load transistors. The pair of load transistors is connected between a supply voltage node and, respectively, to the drain nodes of the input pair of transistors. The CMOS amplifier includes a plurality of second input pairs of transistors to be connected in parallel to the input pair of transistors for increasing the effective width of the resultant transistors. Alternativelty, the CMOS amplifier includes a plurality of second load pairs of transistors to be connected in parallel to the load pair of transistors for increasing the effective width of the resultant transistors. Pairs of path selection switches may be programmably closed for connecting in parallel the selected pairs of transistors.

摘要翻译： 步进增益可变CMOS放大器包括一对输入的晶体管，一个连接在输入晶体管对的一个共同源节点和一个接地节点之间的偏置电流发生器，以及一对负载晶体管。 一对负载晶体管连接在电源电压节点和分别连接到输入晶体管对的漏极节点之间。 CMOS放大器包括多个第二输入对晶体管，以与输入的晶体管对并联连接，以增加所得晶体管的有效宽度。 替代方案，CMOS放大器包括多个第二负载对晶体管，并联连接到晶体管的负载对，以增加所得晶体管的有效宽度。 一对路径选择开关可以可编程地闭合，以并联连接所选择的晶体管对。

公开(公告)号：US20050206450A1

公开(公告)日：2005-09-22

申请号：US10927431

申请日：2004-08-26

申请人： Giacomino Bollati

发明人： Giacomino Bollati

IPC分类号： H03F1/08 ,  H03F1/26 ,  H03F3/45

CPC分类号： H03F3/45085 ,  H03F1/083 ,  H03F1/26 ,  H03F1/48 ,  H03F3/4508 ,  H03F3/45475 ,  H03F3/45484 ,  H03F2200/36 ,  H03F2200/372 ,  H03F2203/45111 ,  H03F2203/45138 ,  H03F2203/45548 ,  H03F2203/45702

摘要： An AC differential amplifier includes a pair of identical differential transconductance stages. Each transconductance stage includes a pair of inputs and a pair of outputs. The pairs of output of the transconductance stages are connected in common, and form a pair of output nodes of the AC differential amplifier. The pair of output nodes is also connected to a supply line through respective load resistors. One input of one transconductance stage is coupled through a capacitive device to an input of the other transconductance stage. The other inputs of the transconductance stages form the input terminals of the AC differential amplifier.

摘要翻译： AC差分放大器包括一对相同的差分跨导级。 每个跨导级包括一对输入和一对输出。 跨导级的输出对共同连接，形成交流差分放大器的一对输出节点。 一对输出节点也通过相应的负载电阻连接到电源线。 一个跨导级的一个输入通过电容器件耦合到另一跨导级的输入端。 跨导级的其他输入构成交流差分放大器的输入端。